Semiconductor integrated circuit capable of compensating for flucuations in power supply voltage level and method of manufacturing the same

• US 6,000,829 A
• Filed: 09/08/1997
• Issued: 12/14/1999
• Est. Priority Date: 09/11/1996
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Kurokawa, Keiichi, Toyonaga, Masahiko, Takahashi, Miwaka, Fukumoto, Minako, Koshita, Noriko
• Primary Examiner(s): Gordon, Paul P.
• Assistant Examiner(s): PATEL, RAMESH B
• Application Number:
  US08/925,437
• Time in Patent Office: 827 Days
• Field of Search: 364/468.01, 364/468.03, 364/468.24, 364/468.28, 364/483, 364/488, 364/489, 364/490, 364/491, 326/33, 326/27, 326/121, 327/540, 327/541, 327/545, 327/546, 700/121, 700/95, 700/97, 700/117
• US Class Current: 700/95
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits

Abstract

In a semiconductor integrated circuit, a CMOS logic circuit receives a voltage from a power-source line, while releasing a current through a ground line. A constant-voltage auxiliary circuit is disposed in parallel with the CMOS logic circuit. The constant-voltage auxiliary circuit receives an output signal from the CMOS logic circuit. The constant-voltage auxiliary circuit consumes power when the output signal from the CMOS logic circuit is stable to maintain a potential difference between the power-source line and the ground line at a specified voltage and halts power consumption when the output signal from the CMOS logic circuit is inverted, i.e., when the potential difference is decreasing, thereby suppressing the decrease of the potential difference. Accordingly, voltage fluctuations on the power-source line are suppressed.

Claims

1. A semiconductor integrated circuit comprising:

a power-source line and a ground line;

a logic circuit portion composing a logic circuit and connected to said power-source line and ground line; and

a constant-voltage auxiliary circuit connected, in parallel with said logic circuit portion, to said power-source line and ground line, said constant-voltage auxiliary circuit consuming power by causing a current to flow from said power-source line to said ground line in a stable state in which an output value from said logic circuit portion does not vary and halting said power consumption when the output value from said logic circuit portion varies.

2. A semiconductor integrated circuit according to claim 1, wherein said constant-voltage auxiliary circuit comprises

a plurality of transistors receiving the output from said logic circuit portion and having voltage characteristics different from each other, said plurality of transistors being connected in parallel to each other.

3. A semiconductor integrated circuit according to claim 2, wherein said constant-voltage auxiliary circuit comprises

a CMOS inverter circuit receiving the output value from said logic circuit portion and connected in parallel to said logic circuit portion.

4. A semiconductor integrated circuit comprising:

a plurality of logic circuits;

a first power-source line connected to each of said logic circuits and carrying a specified power-source voltage;

a second power-source line different from said first power-source line; and

a voltage supplying circuit connected to said first and second power-source lines, said voltage supplying circuit detecting a variation in any of voltages supplied from said first power-source line to said logic circuits from the value of said specified power-source voltage to another value and supplying, upon detection, a voltage from said second power-source line to said first power-source line.

5. A semiconductor integrated circuit according to claim 4, wherein said specified power-source voltage is higher than the ground potential and said voltage supplying circuit supplies the voltage from said second power-source line to said first power-source line when any of the voltages supplied to said logic circuits drops to a value less than said specified power-source voltage.

6. A semiconductor integrated circuit according to claim 5, wherein said voltage supplying circuit is composed of a diode circuit having an input connected to said second power-source line and an output connected to said first power-source line, said voltage supplying circuit supplying a power-source voltage responsive to a voltage drop in each of the logic circuits.

7. A semiconductor integrated circuit according to claim 4, wherein said specified power-source voltage has an extremely small value in the vicinity of the ground potential, said second power-source line is a ground line, and said voltage supplying circuit extracts charges from said first power-source line and releases the extracted charges to said ground line when any of the voltages supplied to said logic circuits increases to a value equal to or more than said extremely small value.

8. A semiconductor integrated circuit according to claim 7, wherein said voltage supplying circuit is composed of a diode circuit having an input connected to said first power source line and an output connected to said ground line, said voltage supplying circuit extracting charges responsive to an increase in the ground voltage in each of the logic circuits.

9. A semiconductor integrated circuit comprising:

an internal semiconductor circuit;

a power source connected to said internal semiconductor circuit;

a first power-source monitor line for monitoring a level of a power-source voltage supplied from said power source to said internal semiconductor circuit;

a second power-source monitor line for monitoring a level of the power-source voltage inside said internal semiconductor circuit when said internal semiconductor circuit is in operation; and

a level-fluctuation compensator connected to said first and second power-source monitor lines, said level-fluctuation compensator detecting fluctuations in the level of the internal power-source voltage when said internal semiconductor circuit is in operation and adjusting, upon detection of fluctuations in the level of the operating voltage, the power-source voltage inside said internal semiconductor circuit to be equal in level to the power-source voltage from said power source.

10. A semiconductor integrated circuit according to claim 9, wherein said power source has a power-source voltage higher than the ground potential and said level-fluctuation compensator comprises:

a charge accumulator for receiving charges supplied from said power source and accumulating therein the received charges; and

a detector for controlling said charge accumulator such that the charges accumulated in said charge accumulator are supplied to said internal semiconductor circuit when the internal power-source voltage drops to a level lower than the power-source voltage from said power source when said internal semiconductor circuit is in operation.

11. A semiconductor integrated circuit according to claim 9, wherein said power source has the ground potential and said level-fluctuation compensator comprises:

a charge releaser for releasing charges to said power source; and

a detector for controlling said charge releaser such that charges are extracted from said internal semiconductor circuit and released to said charge releaser when the internal power-source voltage increases to a level over the ground potential at said power source when said internal semiconductor circuit is in operation.

12. A mask processing method for a semiconductor macro cell, comprising a mask processing step for the semiconductor macro cell using a computer comprising:

a power-source-line-configuration retrieving step of retrieving a power-source-line configuration from an entire region occupied by the cell;

an inverted-geometry generating step of generating an inverted geometry corresponding to said entire region occupied by the cell except for power-source lines and wiring in a wiring layer containing the power-source lines;

a dividing step of dividing said generated inverted geometry into a plurality of geometries;

a mask operation step of adding said post-division inverted geometries to said retrieved power-source-line configuration; and

a power-source-line reducing step of reducing the power-source-line configuration including said additional post-division inverted geometries by the magnitude of a specified minimum wire spacing.