Methods for manufacturing a semiconductor package having a sacrificial layer

• US 6,001,671 A
• Filed: 04/18/1996
• Issued: 12/14/1999
• Est. Priority Date: 04/18/1996
• Status: Expired due to Term

• Current Assignee: Tessera, Inc. (Adeia, Inc.)
• Original Assignee: Tessera, Inc. (Adeia, Inc.)
• Inventors: Fjelstad, Joseph
• Primary Examiner(s): Monin, Jr., Donald L.
• Assistant Examiner(s): Chambliss, Alonzo
• Application Number:
  US08/634,464
• Time in Patent Office: 1,335 Days
• Field of Search: 437/211, 437/207, 437/203, 437/220, 437/915, 437/974, 438/110, 438/112, 438/126, 438/127
• US Class Current: 438/112
• CPC Class Codes: H01L 21/4832 Etching a temporary substrate after encapsulation process to form leads
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/48475 connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49433 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/85001 : involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2224/85051 : Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
• CPC Class Codes: H01L 2224/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10162 : with a square active surface
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A method of manufacturing a semiconductor chip package. A sacrificial layer is used as a base to selectively form an array of conductive pads such that a central region is defined by the pads. A back surface of a semiconductor chip is next attached to the sacrificial layer within the central region between the pads so that the contact bearing surface of the chip faces away from the sacrificial layer. The chip contacts are then electrically connected to respective pads, typically by wire bonding a wire therebetween. A curable, dielectric liquid encapsulant is then deposited on the sacrificial layer such that the pads, electrical connections and chip are fully encapsulated, as by an overmolding operation. The encapsulant is then cured and the sacrificial layer is either completely removed or is selectively removed to expose a surface of the pads for electrical attachment to a PWB and the back surface of the chip for creating a direct thermal path from the chip to the PWB.

Claims

1. A method of making a semiconductor chip package, comprising the steps of:

providing a sacrificial layer;

selectively forming an array of conductive pads on a first surface of the sacrificial layer such that a plurality of central regions are defined by the pads;

attaching back surfaces of a plurality of semiconductor chips to the sacrificial layer within the central regions so that a contact bearing surface of each said chip faces away from the sacrificial layer;

electrically connecting each contact to a respective pad;

depositing curable dielectric material on the first surface of the sacrificial layer such that the pads, electrical connections and chip are each encapsulated and curing the dielectric material; and

removing at least a portion of the sacrificial layer, whereby a plurality of semiconductor chip packages are manufactured simultaneously using the same sacrificial layer, and wherein said curable dielectric material is deposited so as to form a unitary mass covering said plurality of chips, the method further comprising the step of separating at least some of the packages after the removing step by severing said unitary mass of dielectric material.

2. The method as claimed in claim 1, wherein the separating step provides a plurality of individual chip packages.

3. The method as claimed in claim 1, wherein the separating step provides a plurality of chip modules including at least two chips.

9. The method as claimed in claim 1, wherein the pads are arranged in a grid array around each said central region.

20. The method as claimed in claim 3, further comprising the step of electrically connecting at least some of the pads associated with a first chip with the pads associated with a second chip within a particular module.

21. The method as claimed in claim 20, further comprising the step of disposing a sheet-like dielectric layer atop the first surface of the sacrificial layer prior to the pad forming step, wherein the step of electrically connecting pads of a first chip to pads of a second chip includes providing conductive traces on the dielectric layer interconnecting the respective pads.

22. The method as claimed in claim 1, wherein the sacrificial layer is selected from the group consisting of copper, aluminum, iron, steel, bronze, brass, polyimide, polyetherimide, fluropolymer and alloys and combinations thereof.

23. The method as claimed in claim 1, wherein the electrically connecting step includes wire-bonding the contacts to respective pads.

24. The method as claimed in claim 1, wherein the removing step includes etching the sacrificial layer.

25. The method as claimed in claim 1, wherein the removing step includes the provision of a direct thermal path between the back surface of the chip and a heat sink.

4. A method of making a semiconductor chip package, comprising the steps of:

providing a sacrificial layer;

selectively forming an array of conductive pads on a first surface of the sacrificial layer such that a central region is defined by the pads;

attaching a back surface of a semiconductor chip to the sacrificial layer within the central region so that a contact bearing surface of the chip faces away from the sacrificial layer;

electrically connecting each contact to a respective pad;

depositing curable dielectric material on the first surface of the sacrificial layer such that the pads, electrical connections and chip are each encapsulated and curing the dielectric material; and

removing at least a portion of the sacrificial layer,

the method further comprising the step of removing portions of the sacrificial layer prior to the pad forming step so as to create a plurality of cavities within the sacrificial layer, wherein the pad forming step further includes forming each conductive pad within a respective cavity such that the conductive pad material substantially fills the cavity.

5. The method as claimed in claim 4, wherein the step of removing portions of the sacrifical layer includes selectively etching the sacrifical layer.

6. The method as claimed in claim 4, wherein the pad forming step further includes the step of forming a first conductive bump within the cavity and a post projecting upwardly from the first conductive bump and so that each bump has a flange portion which extends beyond the width or diameter of the post.

7. The method as claimed in claim 6, wherein the pad forming method includes integrally forming a second conductive bump on a top portion of each post.

8. The method as claimed in claim 7, wherein the integral combination of the first and second bump and the post constituting each pad is rivet-shaped, and has bumps projecting outwardly from a post at the top and bottom of the pad, and wherein said curable dielectric material penetrates around the post of each bump so that the bump at the top of each pad is embedded in the dielectric material and holds the pad in place within the dielectric material.

10. A method of making a semiconductor chip package, comprising the steps of:

providing a sacrificial layer;

selectively forming an array of conductive pads on a first surface of the sacrificial layer such that a central region is defined by the pads;

attaching a back surface of a semiconductor chip to the sacrificial layer within the central region so that a contact bearing surface of the chip faces away from the sacrificial layer;

electrically connecting each contact to a respective pad;

depositing curable dielectric material on the first surface of the sacrificial layer such that the pads, electrical connections and chip are each encapsulated and curing the dielectric material so as to form a mass of cured dielectric material having a bottom surface in contact with the sacrificial layer and a top surface remote from the sacrificial layer; and

removing at least a portion of the sacrificial layer;

wherein at least some of the pads have conductive protrusions which extend upwardly to said top surface of said mass of dielectric material.

11. The method as claimed in claim 10, wherein the pad forming step further includes the step of forming pads of different heights from the sacrificial layer.

12. The method as claimed in claim 10, wherein the conductive protrusions extend substantially orthogonal with respect to the contact bearing surface of the chip.

13. A method of making a semiconductor chip package, comprising the steps of:

providing a sacrificial layer;

selectively forming an array of conductive pads on a first surface of the sacrificial layer such that a central region is defined by the pads;

attaching a back surface of a semiconductor chip to the sacrificial layer within the central region so that a contact bearing surface of the chip faces away from the sacrificial layer;

electrically connecting each contact to a respective pad;

depositing curable dielectric material on the first surface of the sacrificial layer such that the pads, electrical connections and chip are each encapsulated and curing the dielectric material; and

removing at least a portion of the sacrificial layer;

wherein the pad forming step further includes the step of disposing a dielectric base material between the sacrificial layer and the conductive pads such that the pads are formed on and supported by the base material.

14. The method as claimed in claim 13, further comprising the steps of drilling apertures through the cured dielectric material such that the aperture side walls extend through the package from a top surface to a bottom surface thereby creating a via through at least some of the conductive pads, and metallizing the side walls of the apertures.

15. The method as claimed in claim 14, further comprising the step of filling the metallized apertures with conductive material.

16. The method as claimed in claim 14, wherein the side walls of the apertures are substantially orthogonal with respect to the contact bearing surface of the chip.

17. A method of making a semiconductor chip package, comprising the steps of:

providing a sacrificial layer;

selectively forming an array of conductive pads on a first surface of the sacrificial layer such that a central region is defined by the pads;

attaching a back surface of a semiconductor chip to the sacrificial layer within the central region so that a contact bearing surface of the chip faces away from the sacrificial layer;

electrically connecting each contact to a respective pad;

depositing curable dielectric material on the first surface of the sacrificial layer such that the pads, electrical connections and chip are each encapsulated and curing the dielectric material; and

removing at least a portion of the sacrificial layer wherein the attaching step further includes the step of attaching a microelectronic component to the contact bearing surface of the chip, wherein the electrically connecting step further includes connecting the contacts on the component to a respective pad.

18. The method as claimed in claim 17, wherein the component includes a second semiconductor chip, wherein attaching step further includes attaching a back surface of the second chip to the contact bearing surface of the first chip.

19. The method as claimed in claim 17, wherein electrically connecting step further includes connecting at least one contact on the component to a respective contact on the chip.

26. A method of making a semiconductor chip package, comprising the steps of:

providing an electrically conductive sacrificial layer;

selectively forming an protruding array of conductive pads and a protruding central base in a first surface of the sacrificial layer such that the central base is located within a region defined by the pads, the pad forming step including the step of selectively removing material from the first surface of the sacrificial layer;

attaching a back surface of a semiconductor chip to the central base so that the contact bearing surface of the chip faces away from the sacrificial layer;

electrically connecting each contact to a respective pad;

depositing curable dielectric material on the first surface of the sacrificial layer such that the pads, base, electrical connections and chip are each encapsulated and curing the dielectric material; and

selectively removing portions of the sacrificial layer such that the pads and central base are exposed on a bottom surface of the package.

27. The method as claimed in claim 26, wherein a plurality of semiconductor chip packages are manufactured simultaneously using the same sacrificial layer, the method further comprising the step of separating at least some of the packages after the selectively removing step.

28. The method as claimed in claim 27, wherein the separating step provides a plurality of individual chip packages.

29. The method as claimed in claim 27, wherein the separating step provides a plurality of chip modules including at least two chips.

30. The method as claimed in claim 26, wherein the pad forming step includes selectively etching the first surface of the sacrificial layer.

31. The method as claimed in claim 26, wherein the removing step includes selectively etching a second exposed surface of the sacrificial layer.

32. The method as claimed in claim 31, wherein the central base protrudes out from the bottom surface of the package.

33. The method as claimed in claim 32, wherein the removing step includes the provision of a direct thermal path between the back surface of the chip and a heat sink.

34. The method as claimed in claim 26, wherein the electrically connecting step includes wire-bonding the contacts to respective pads.

35. A method of making a semiconductor chip package, comprising the steps of:

providing a sheet-like dielectric layer;

selectively forming an array of conductive pads and a central base on a first surface of the dielectric layer such that the central base is located within a region defined by the pads;

attaching a back surface of a semiconductor chip to the central base so that the contact bearing surface of the chip faces away from the dielectric layer;

electrically connecting each contact to a respective pad;

depositing curable dielectric material on the first surface of the dielectric layer such that the pads, electrical connections and chip are each encapsulated and curing the dielectric material; and

selectively removing portions of the dielectric layer such that portions of the pads and central base are exposed on a bottom surface of the package.

36. The method as claimed in claim 35, wherein the removing step includes selectively etching the dielectric layer.

37. The method as claimed in claim 35, wherein the removing step includes selectively applying focused radiant energy to the dielectric layer.

38. The method as claimed in claim 35, wherein the removing step includes the provision of a direct thermal path between the back surface of the chip and a heat sink.

39. The method as claimed in claim 35, wherein the electrically connecting step includes wire-bonding the contacts to respective pads.

40. The method as claimed in claim 35, wherein a plurality of semiconductor chip packages are manufactured simultaneously using the same dielectric layer, the method further comprising the step of separating at least some of the packages after the selectively removing step.

41. The method as claimed in claim 40, wherein the separating step provides a plurality of individual chip packages.

42. The method as claimed in claim 40, wherein the separating step provides a plurality of chip modules including at least two chips.

43. The method as claimed in claim 42, further comprising the step of electrically connecting at least some of the pads associated with a first chip with the pads associated with a second chip within a particular module.

44. The method as claimed in claim 43, wherein the step of electrically connecting the pads includes providing conductive traces on the dielectric layer interconnecting the respective pads.