Insulated gate semiconductor device

• US 6,001,678 A
• Filed: 09/25/1997
• Issued: 12/14/1999
• Est. Priority Date: 03/14/1995
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Takahashi, Hideki
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Hack, Jonathan
• Application Number:
  US08/937,163
• Time in Patent Office: 810 Days
• Field of Search: 438/238, 438/243, 438/245, 438/271
• US Class Current: 438/238
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

It is an object to obtain an insulated gate semiconductor device with an unreduced current value capable of being turned off while adopting structure for reducing the ON voltage, and a manufacturing method thereof. An N layer (43) is provided in close contact on a surface of an N^- layer (42), a P base layer (44) is provided in close contact on the surface of the N layer (43), and a trench (47) which passes at least through the P base layer (44) is provided, and a gate electrode (49) is provided in the trench (47) through a gate insulating film (48). The carrier distribution of the N^- layer (42) becomes closer to the carrier distribution of a diode, and an ON voltage is decreased and a current value capable of being turned off is not decreased when turning off. Accordingly, there are provided an insulated gate semiconductor device with low power consumption, small size, large capacity and high reliability.

Claims

1. A method of manufacturing an insulate gate semiconductor device, comprising:

a substrate forming step of forming a semiconductor substrate defining first and second main surfaces and having a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type with a lower impurity concentration, said first semiconductor layer being exposed in said first main surface and said second semiconductor layer being exposed in said second main surface;

a first implantation step of implanting and diffusing impurity of the second conductivity type to an impurity concentration higher than the impurity concentration of said second semiconductor layer into said second main surface of said semiconductor substrate to form a third semiconductor layer of the second conductivity type in a surface portion of said second semiconductor layer;

a second implantation step of implanting and diffusing impurity of the first conductivity type in a surface of said third semiconductor layer to form a fourth semiconductor layer of the first conductivity type in a surface portion of said third semiconductor layer, wherein said third semiconductor layer is so formed as to be thinner after forming said fourth semiconductor layer than said second semiconductor layer remaining;

a third implantation step of selectively implanting and diffusing impurity of the second conductivity type in a surface of said fourth semiconductor layer to selectively form a fifth semiconductor layer of the second conductivity type in a surface portion of said fourth semiconductor layer;

a first removing step of forming a shield film having an opening surrounding a part of a surface of said fifth semiconductor layer on the surface of said fourth semiconductor layer and the surface of said fifth semiconductor layer and selectively removing a portion of said fifth semiconductor layer, a portion of said fourth semiconductor layer and a portion of said third semiconductor layer using the shield film as a mask to form a trench with a depth extending at least into said third semiconductor layer through said fourth semiconductor layer, and removing said shield film after that;

a first step forming an insulating film on surfaces of said trench, said fourth semiconductor layer and said fifth semiconductor layer;

a first provision step of providing a conductor on said insulating film so as to fill said trench;

a second removing step of uniformly removing said provided conductor to the opening of said trench so as to leave the conductor in said trench as a control electrode;

a second provision step of providing an insulating layer on the surface of said insulating film and a surface of the conductor buried in said trench;

a third removing step of selectively removing said insulating layer and said insulating film in a region covering the surface of said fourth semiconductor layer and a part of the surface of said fifth semiconductor layer;

a step of providing a conductor on the surfaces of said fourth and fifth semiconductor layers exposed by said third removing step to form a first main electrode; and

a step of providing a conductor on said first main surface of said semiconductor substrate to form a second main electrode.

2. The method of manufacturing the insulated gate semiconductor device according to claim 1, wherein, in said first removing step, said trench is formed with a depth extending also through said third semiconductor layer.

3. The method of manufacturing the insulated gate semiconductor device according to claim 1, wherein said trench is formed with a depth which stays in said third semiconductor layer in said first removing step.

4. The method of manufacturing the insulated gate semiconductor device according to claim 3, wherein, in said first removing step, said trench is formed with a depth so that a thickness of said third semiconductor layer between the bottom of said trench and said second semiconductor layer is not more than a critical thickness at which a rapid decrease appears in a breakdown voltage of said insulated gate semiconductor device with an increase in the thickness.

5. The method of manufacturing the insulated gate semiconductor device according to claim 1, wherein said substrate forming step comprises the steps of;

preparing a semiconductor substrate body of the first conductivity type having two main surfaces, and

providing a semiconductor layer of the second conductivity type with a low impurity concentration by the epitaxial growth on one of the main surfaces of said semiconductor substrate body to form said second semiconductor layer.

6. The method of manufacturing the insulated gate semiconductor device according to claim 1, wherein said substrate forming step comprises the steps of;

preparing a semiconductor substrate body of the second conductivity type with a low impurity concentration having two main surfaces,

implanting impurity of the first conductivity type into one of the main surfaces of said semiconductor substrate body; and

diffusing said impurity implanted into said one main surface to form said first semiconductor layer of the first conductivity type.

7. The method of manufacturing the insulated gate semiconductor device according to claim 6, wherein said step of implanting the impurity of the first conductivity type comprises the steps of,

selectively implanting impurity of the first conductivity type into said one main surface of said semiconductor substrate body.

8. The method of manufacturing the insulated gate semiconductor device according to claim 1, wherein said semiconductor substrate formed in said substrate forming step further comprises a sixth semiconductor layer of the second conductivity type with a high impurity concentration interposed between said first semiconductor layer and said second semiconductor layer.

9. The method of manufacturing the insulated gate semiconductor device according to claim 8, wherein said substrate forming step comprises the steps of;

preparing a semiconductor substrate body of the first conductivity type having two main surfaces, and

sequentially forming said sixth semiconductor layer and said second semiconductor layer by the epitaxial growth on one of the main surfaces of said semiconductor substrate body.

10. The method of manufacturing the insulated gate semiconductor device according to claim 8, wherein said substrate forming step comprises the steps of;

preparing a semiconductor substrate body of the second conductivity type with a low impurity concentration having two main surfaces,

forming said sixth semiconductor layer by implanting impurity of the second conductivity type and then diffusing on one of the main surfaces of said semiconductor substrate body, and

implanting and then diffusing impurity of the first conductivity type in a surface of said sixth semiconductor layer to form said first semiconductor layer.

11. The method of manufacturing the insulated gate semiconductor device according to claim 1, wherein said step of forming said first semiconductor layer comprises the steps of;

selectively implanting impurity of the first conductivity type into the surface of said sixth semiconductor layer and

diffusing said impurity selectively implanted into the surface of said sixth semiconductor layer.

12. The method of manufacturing the insulated gate semiconductor device according to claim 1, wherein, if the impurity concentrations in said second semiconductor layer, said third semiconductor layer and said fourth semiconductor layer are taken as C₂, C₃, C₄, respectively, said first implantation step and said second implantation step are carried out so that the relation thereof is C₂ <

C₃ <

C₄.

13. The method of manufacturing the insulated gate semiconductor device according to claim 1, wherein said third implantation step comprises steps of:

forming a resist pattern selectively having an opening in a surface of said fourth semiconductor layer on the surface of said fourth semiconductor layer; and

,

implanting and diffusing impurity of the second conductivity type using the resist pattern as a mask to selectively form said fifth semiconductor layer of the second conductivity type in a surface portion of said fourth semiconductor layer.

14. The method of manufacturing the insulated gate semiconductor device according to claim 1, wherein said third removing step comprises steps of:

forming a resist pattern having an opening surrounding the surface of said fourth semiconductor layer and a part of the surface of said fifth semiconductor layer on a surface of said insulating layer; and

,

selectively removing said insulating layer and said insulating film using the resist pattern as a mask.

15. The method of manufacturing the insulated gate semiconductor device according to claim 7, wherein said step of implanting the impurity of the first conductivity type further comprises the step of,

forming a resist pattern having a selectively formed opening on said one main surface of said semiconductor substrate body, and

said step of selectively implanting said impurity comprises the step of selectively implanting said impurity of the first conductivity type into said one main surface of said semiconductor substrate body using said resist pattern formed on said one main surface as a mask.

16. The method of manufacturing the insulated gate semiconductor device according to claim 11, wherein said step of forming said first semiconductor layer further comprises the step of;

forming a resist pattern having a selectively formed opening on the surface of said sixth semiconductor layer, and

said step of selectively implanting said impurity comprises the step of selectively implanting said impurity of the first conductivity type into the surface of said sixth semiconductor layer using said resist pattern formed on the surface of said sixth semiconductor layer as a mask.