Method of making a metal to metal antifuse

• US 6,001,693 A
• Filed: 09/01/1995
• Issued: 12/14/1999
• Est. Priority Date: 10/06/1994
• Status: Expired due to Term

• Current Assignee: Microsemi SoC Corp. (Microchip Technology Incorporated)
• Original Assignee: Elaine K. Poon, James B. Kruger, Leuh Fang, Shih-Oh Chen, Yen Yeouchung
• Inventors: Kruger, James B., Poon, Elaine K., Fang, Leuh, Yeouchung, Yen, Chen, Shih-Oh
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Owens, Douglas W.
• Application Number:
  US08/999,970
• Time in Patent Office: 1,565 Days
• Field of Search: 438/281, 437/195
• US Class Current: 438/281
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The antifuse structure of the present invention includes a bottom planarized electrode, an ILD disposed over the bottom electrode, an antifuse cell opening in and through the ILD exposing the bottom electrode, a first barrier metal layer disposed in the antifuse cell opening to protect the antifuse material layer from diffusion from the bottom electrode and to form an effective bottom electrode of reduced area, hence reducing the capacitance of the device, an antifuse material layer disposed in the antifuse cell opening and over the first barrier metal layer, a second barrier metal layer disposed over the antifuse material layer, and a top electrode disposed over the second barrier metal layer.

Claims

1. A process for fabricating a metal-to-metal antifuse comprising the following steps:

(a) forming a bottom electrode having an upper surface over an insulating portion of a microcircuit structure;

(b) forming an interlayer dielectric layer over said bottom electrode;

(c) etching an antifuse cell opening in and through said interlayer dielectric layer so as to expose a portion of said upper surface of said bottom electrode;

(d) blanket depositing a first barrier metal layer over said interlayer dielectric layer and in said antifuse cell opening and over and in physical and electrical contact with said bottom electrode;

(e) spin depositing a layer of photoresist over said first barrier metal layer;

(f) etching back said photoresist and said first barrier metal layer so as to leave only a cup-shaped portion of said first barrier metal layer disposed in said antifuse cell opening;

(g) stripping the remaining photoresist from within said cup-shaped portion;

(h) depositing an antifuse material layer over and in said cup-shaped portion and over said interlayer dielectric layer;

(i) depositing a second barrier metal layer over said antifuse material layer;

(j) patterning and etching said antifuse material layer and said second barrier metal layer; and

(k) forming a top electrode over said second barrier metal layer.

2. A process for fabricating a metal-to-metal antifuse according to claim 1 further including the following step which takes place between step (j) and step (k):

(l) forming a spacer of an insulating material adjacent edges formed by step (j) in said antifuse material layer and said second barrier metal layer.

3. A process for fabricating a metal-to-metal antifuse according to claim 1 further including the following step which takes place between step (g) and step (h):

(l) forming spacers of an insulating material in internal corners formed in said cup-shaped portion and between said cup-shaped portion and said antifuse cell opening.

4. A process for fabricating a metal-to-metal antifuse according to claim 2 further including the following step which takes place between step (g) and step (h):

(m) forming spacers of an insulating material in internal corners formed in said cup-shaped portion and between said cup-shaped portion and said antifuse cell opening.