Electronic device pad relocation, precision placement, and packaging in arrays

• US 6,002,163 A
• Filed: 12/21/1998
• Issued: 12/14/1999
• Est. Priority Date: 01/02/1998
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Wojnarowski, Robert John
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): THAI, LUAN C
• Application Number:
  US09/217,334
• Time in Patent Office: 358 Days
• Field of Search: 257/774, 257/777, 257/778, 257/688, 257/689, 257/618, 257/620, 257/619, 257/621, 257/622, 257/623, 438/113, 438/462, 438/460, 438/463, 438/464, 438/666, 438/667, 29/759, 29/830
• US Class Current: 257/620
• CPC Class Codes: H01L 21/3043 Making grooves, e.g. cutting
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05669 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

Top die pads are electrically relocated by forming holes through a semiconductor wafer between device active regions. An electrically insulating layer is formed over all exposed surfaces of the wafer, including within the holes, and openings are made in the insulating layer for access to the top interconnection pads. The wafer and holes are metallized and patterned to form bottom interconnection pads electrically connected to corresponding top interconnection pads by metallization extending within the holes. A dicing saw having a kerf width less than the diameter of the holes is employed to separate the individual devices. For accurate position alignment of repatterned die, an alignment structure, such as projecting pins or an egg crate structure, engages the die, and alignment pads can be patterned on the die.

Claims

1. An array of closely-spaced devices comprising:

a plurality of electrical devices, each electrical device including

top interconnection pads on a front major surface,

an electrically insulating layer on the front major surface and a rear major surface, and a portion of at least one side surface, with openings in the insulating layer for access to the top interconnection pads,

patterned metallization on the front and rear major surfaces and over the portion of at least one side surface forming bottom interconnection pads and alignment pads on the rear major surface, the bottom interconnection pads electrically connected to corresponding top interconnection pads by metallization extending over the electrically insulating layer on the portion of the at least one side surface; and

a multi-chip module having a high density interconnect overcoat structure with at least two electrical connection pads positioned for mating with the alignment pads and a rigid alignment structure projecting from the multi-chip module for mechanical engagement with the electrical devices and providing accurate position alignment.

2. The array of claim 1, further including solder for attaching the alignment pads of the electrical devices to the at least two electrical connection pads of the multi-chip module.

3. The array of claim 1, wherein the rigid alignment structure comprises a set of pins or a grid-like structure.

4. An array of closely-spaced imaging or display devices comprising:

a plurality of imaging or display devices, each device including

top interconnection pads on a front major surface,

an electrically insulating layer on the front major surface and a rear major surface, and a portion of at least one side surface, with openings in the insulating layer for access to the top interconnection pads,

patterned metallization on the front and rear major surfaces and over the portion of at least one side surface forming bottom interconnection pads and alignment pads on the rear major surface, the bottom interconnection pads electrically connected to corresponding top interconnection pads by metallization extending over the electrically insulating layer on the portion of the at least one side surface;

an optically transparent substrate, the devices being positioned front major surface down on the optically transparent substrate; and

a multilayer interconnect structure overlying the rear major surfaces of the devices in electrical connection with the bottom interconnection pads.

5. The array of claim 4, wherein the optically transparent substrate is rigid.

6. The array of claim 4, wherein the optically transparent substrate comprises a stretched polymer film.

7. The array of claim 4, which further includes a molding material to fix the devices in place.

8. An array of closely-spaced devices comprising:

a plurality of electrical devices, each electrical device including

top interconnection pads on a front major surface,

an electrically insulating layer on the front major surface and a rear major surface, and a portion of at least one side surface, with openings in the insulating layer for access to the top interconnection pads,

patterned metallization on the front and rear major surfaces and over the portion of at least one side surface forming bottom interconnection pads and alignment pads on the rear major surface, the bottom interconnection pads electrically connected to corresponding top interconnection pads by metallization extending over the electrically insulating layer on the portion of the at least one side surface;

a substrate comprising a stretched polymer film, the devices being positioned and attached front major surface down on the substrate; and

a multilayer interconnect structure overlying the rear major surfaces of the devices in electrical connection with the bottom interconnection pads, the substrate and the multilayer interconnect structure being curved to establish an array curvature.

9. A array for a multi-device electronic package including a plurality of devices having major surfaces, with interconnection pads on one of the major surfaces, said array comprising:

a substrate having a rigid alignment structure thereon projecting from the substrate for mechanical engagement with the devices, the devices being positioned and attached to the substrate with the interconnection pads facing up, whereby the rigid alignment structure provides accurate position alignment; and

a multilayer interconnect structure overlying the devices and interconnecting selected ones of the interconnection pads.

10. The array of claim 9, wherein the rigid alignment structure formed is a set of pins or a grid-like structure.