Substrate structure and method for improving attachment reliability of semiconductor chips and modules
First Claim
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1. An adhesion pad for a substrate comprising:
- a first flat planar layer having a perimeter on said substrate;
a second flat planar layer on said first flat planar layer disposed within said perimeter of said first flat planar layer to form at least one raised structure with a substantially vertical sidewall on said first flat planar layer, said first and second flat planar layers being wettable for directly contacting a mass of solder;
said first flat planar layer and said second flat planar layer are substantially circular, each having a respective diameter, said diameter of said second flat planar layer is in the range of 30-70% of said diameter of said first flat planar layer, said first flat planar layer has a thickness at least 10% of said diameter of said first flat planar layer;
said substrate is one of the group consisting of an organic chip carrier, a ceramic chip carrier, and an organic circuit board, andsaid thickness of said first flat planar layer is in the range of 33-41 μ
m (0.0013 to 0.0016 inches) and said second flat planar layer has a thickness in the range of 63-76 μ
m (0.0025 to 0.0030 inches).
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Abstract
An adhesion pad for adhering a semiconductor chip or a ball grid array module to a supporting substrate includes a stepped or tapered structure. The structure is composed of at least one solder wettable metal or alloy layer having solder deposited thereon. The stepped or tapered structure prevents a fatigue crack from propagating in the X-Y plane above the adhesion pad.
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Citations
6 Claims
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1. An adhesion pad for a substrate comprising:
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a first flat planar layer having a perimeter on said substrate; a second flat planar layer on said first flat planar layer disposed within said perimeter of said first flat planar layer to form at least one raised structure with a substantially vertical sidewall on said first flat planar layer, said first and second flat planar layers being wettable for directly contacting a mass of solder; said first flat planar layer and said second flat planar layer are substantially circular, each having a respective diameter, said diameter of said second flat planar layer is in the range of 30-70% of said diameter of said first flat planar layer, said first flat planar layer has a thickness at least 10% of said diameter of said first flat planar layer; said substrate is one of the group consisting of an organic chip carrier, a ceramic chip carrier, and an organic circuit board, and said thickness of said first flat planar layer is in the range of 33-41 μ
m (0.0013 to 0.0016 inches) and said second flat planar layer has a thickness in the range of 63-76 μ
m (0.0025 to 0.0030 inches). - View Dependent Claims (2, 3, 4, 5, 6)
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Specification