Trimming circuit

• US 6,002,261 A
• Filed: 10/08/1997
• Issued: 12/14/1999
• Est. Priority Date: 10/09/1996
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Goldman, Richard
• Primary Examiner(s): Do, Diep N.
• Application Number:
  US08/947,436
• Time in Patent Office: 797 Days
• Field of Search: 324/537, 324/550, 324/555, 340/638, 365/96, 365/201, 365/225.7, 257/50, 257/529, 257/530, 257/567, 327/525, 327/526, 326/38, 438/467
• US Class Current: 324/550
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters

Abstract

To monitor the state of an antifuse capacitor, a transistor is connected to the capacitor such that it saturates only when the capacitor is not blown. Monitoring the base current of the transistor allows the state of the capacitor to be monitored without needing to use a conventional high-voltage comparator.

Claims

1. A trimming circuit, comprising an antifuse capacitor, the antifuse capacitor having a first terminal connected to a ground rail, and a second terminal to which a voltage may be selectively applied to blow the capacitor, the circuit further comprising:

a first transistor (T5) connected between a first supply voltage rail and the second terminal of the capacitor;

a current source, connected to the second terminal of the capacitor is not blown, the first transistor is saturated and draws a large base current, whereas, when the antifuse capacitor is blown, the first transistor is not saturated and draws a smaller base current; and

means for monitoring the base current of the first transistor to determine when the first transistor is saturated.

2. A trimming circuit as claimed in claim 1, wherein the current source comprises a first current mirror circuit comprising a first pair of transistors (T3, T4), a first transistor (T4) of the pair having its collector-emitter path connected between the second terminal of the capacitor and a second supply voltage which is sufficient to blow the antifuse capacitor, and a second transistor (T3) of the pair having its collector-emitter path connected between the first supply voltage rail and a second supply voltage through a further transistor (T1) which is controlled from an input terminal of the circuit.

3. A trimming circuit as claimed in claim 1, wherein the base terminal of the first transistor (T5) is connected to a current sink (T11), and to the base terminal of a second transistor (T12), such that, when the first transistor (T5) is unsaturated, its base current flows through the current sink (T11), and the second transistor (T12) is switched off, and, when the first transistor (T5) is saturated, the second transistor (T12) is switched on.

4. A trimming circuit as claimed in claim 3, wherein the first transistor forms a current mirror circuit with a third transistor (T8), the bases of the first and third transistors being connected together, and the circuit comprises means for drawing a reference current through the third transistor (T8).

5. A trimming circuit, comprising an antifuse capacitor, and means for selectively applying a suitable voltage thereto to blow the antifuse capacitor, and further comprising:

a first current mirror circuit, comprising first (T5) and second (T8) transistors, the first transistor (T5) being connected between one terminal of the antifuse capacitor and a supply voltage rail;

a third transistor (T10), connected to the bases of the first and second transistors (T5, T8), such that the base currents of the first and second transistors flow therethrough;

a current sink (T11), connected to receive the current flowing through the third transistor (T10);

a fourth transistor (T12), with its collector-emitter path connected in series with a load element (R3) between the supply voltage rail and a ground rail, and with its base terminal connected to the connection of the third transistor (T10) and the current sink (T11); and

an output terminal (I3) located between the load element and through transistor (T12).

6. A trimming circuit as claimed in claim 5, wherein, when the antifuse capacitor is not blown, the first transistor (T5) is saturated and therefore has a large base current, which causes the base terminal of the fourth transistor (T12) to receive a current which switches the fourth transistor (T12) on, and therefore causes the voltage at the output terminal to approach ground voltage,

whereas, when the antifuse capacitor is blown, the first transistor (T5) is not saturated, and therefore has a smaller base current, which flows through the current sink (T11), so that the base terminal of the fourth transistor (T12) receives no current, so that the fourth transistor (T12) is switched off, and therefore causes the voltage at the output terminal to go high.

7. A method of monitoring the state of an antifuse capacitor, the antifuse capacitor having a first terminal connected to a ground rail, and a second terminal to which a voltage may be selectively applied to blow the capacitor, the circuit further comprising a current source, connected to the second terminal of the capacitor, the method comprising:

connecting a first transistor (T5) between a first supply voltage rail and the second terminal of the capacitor, such that, when the antifuse capacitor is not blown, the first transistor is saturated and draws a large base current, whereas, when the antifuse capacitor is blown, the first transistor (T5) is not saturated and draws a smaller base current; and

monitoring the base current of the first transistor (T5) to determine when the first transistor (T5) is saturated.