FPGA with conductors segmented by active repeaters

• US 6,002,268 A
• Filed: 11/26/1997
• Issued: 12/14/1999
• Est. Priority Date: 01/08/1993
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: DynaChip Corporation
• Inventors: West, Burnell G, Vora, Madhukar, Sasaki, Paul Takao
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Chang, Daniel D.
• Application Number:
  US08/978,691
• Time in Patent Office: 748 Days
• Field of Search: 326/38, 326/39, 326/40, 326/41
• US Class Current: 326/41
• CPC Class Codes: H03K 17/6257 with several inputs only combined with selecting means
• CPC Class Codes: H03K 17/6264 using current steering means
• CPC Class Codes: H03K 17/6285 with several outputs only combined with selecting means
• CPC Class Codes: H03K 17/6292 using current steering means
• CPC Class Codes: H03K 19/01759 with a bidirectional operation
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters

Abstract

An interface circuit for use in the layout of padframe interface circuits for field programmable gate arrays having a plurality of I/O cells each of which may be programmed as an input or an output (or both) and a programmable connection matrix which provide programmable pathways between the data output signals generated by the core array of logic blocks and I/O cells programmed as outputs and provide programmable pathways between I/O cells programmed as inputs and data input conductors going into the core array. The interface circuits are all substantially identical in structure, and each includes a sufficient number of power and ground connections to supply adequate current to the number of I/O cells the interface has. Each interface circuit also includes at least one and preferably two open spaces into which conductive paths may be laid out to carry power to the core array or carry dedicated signals to circuits other than the core which also reside on the integrated circuit. Because of the substantially identical structure of each interface and the preservation of ratios between I/O cells, power and ground connections and open slots, larger or smaller core arrays may be accommodated by cutting and pasting additional interface circuits into the layout thereby substantially decreasing design, placement and layout time and time to market for introduction of new FPGAs in a family with larger core arrays. The regular repeatable structure of RIU'"'"'s simplifies software development for products within the family and as such contributes to faster "time to market".

Claims

1. A differential signal conductor in a field programmable gate array having first and second conductors carrying complementary logic signals and segmented into first and second segments by a programmable buffer amplifier with an emitter follower output stage, both said buffer amplifier and said emitter follower being coupled to high and low rail conductors coupled to an external power supply when said field programmable gate array is in operation and utilizing bipolar devices coupled as a differential pair having a common emitter node which is coupled to said low rail of said power supply through a current source and a first MOS steering device, said common emitter node being coupled to said high rail of said power supply through a second MOS steering device, said first and second MOS steering devices having gate terminals coupled to receive an enable signal that activates said differential pair, said differential pair having collector terminals coupled to said second segment of said differential signals conductor via said emitter follower output stage, said collector terminals also coupled to said high rail of said power supply through load resistors, and having base inputs coupled to receive said complementary logic signals from said first segment such that there is no direct conductive path between said first and second line segments but such that any complementary logic signal on said first line segment which has had its rise time degraded by the effect of parasitic capacitance and/or parasitic resistance has its rise time reconstructed on said second line segment as a complementary logic signal with a speeded up rise time.

2. A field programmable gate array having a core array of programmable logic blocks each having data inputs and data outputs each of which is programmably coupled through one or more programmable active repeaters to one or more selected individual signal lines of at least one of a plurality of vertical and horizontal buses, said vertical and horizontal buses comprised of a plurality of individual conductive signal lines each of which are divided into segments by a plurality of active repeaters, said vertical and horizontal buses intersecting at a plurality of intersections, each intersection being a programmable connection matrix which is has a plurality of programmable connection circuits therein each said programmable connection circuit being an active repeater which functions to regenerate the signals on preselected individual conductive signal lines of said horizontal buses on preselected individual conductive signal lines of said vertical buses with speeded up rise and fall times relative to the degraded rise and fall times of input pulses to each said activer repeater so as enable either unidirectional or bidirectional communication, said programmable logic blocks being coupled to each other through interconnections comprised of individual segments of said individual conductive signal lines of said vertical and horizontal buses and selected active repeaters which are programmed to couple signals between the appropriate segments to make the necessary connections to implement a desired functionality for said field programmable gate array, and wherein each said active repeater is a transistor amplifier with an output stage which is optimally sized to drive only the load on the line segment or logic block input coupled to the output of said output stage to achieve a desired switching speed for said field programmable gate array.

3. The field programmable gate array of claim 2 wherein at least some of said active repeaters and programmable drivers are optimally structured in integrated circuit form to implement a totem pole type, push-pull output stage with the push-pull transistors optimally sized in a ratioless configuration both to drive a known capacitive load to make logic transitions with a desired speed and to preserve symmetrical rise and fall times.

4. A field programmable gate array comprising:

a core array of programmable logic blocks each having data inputs and data outputs which are programmably coupled through one or more programmable active repeaters to one or more selected individual signal lines of at least one of a plurality of vertical and horizontal buses,

said vertical and horizontal buses comprised of a plurality of individual conductive signal lines each of which are divided into segments by a plurality of active repeaters,

said vertical and horizontal buses intersecting at a plurality of intersections, each intersection being a programmable connection matrix which has a plurality of programmable connection circuits therein,

each said programmable connection circuit being an active repeater which functions to programmably regenerate signals from one or more preselected individual conductive signal lines of said horizontal buses on one or more preselected individual conductive signal lines of said vertical buses for either unidirectional or bidirectional communication,

said programmable logic blocks being coupled to each other through interconnections comprised of individual segments of said individual conductive signal lines of said vertical and horizontal buses and selected active repeaters which are programmed to drive signals between the appropriate segments to make the necessary connections to implement a desired functionality for said field programmable gate array,

and further comprising a plurality of I/O cells surrounding said core array,

each I/O cell being programmable as a data input or a data output, or both said I/O cells programmed as both data inputs and data outputs functioning to return data emerging from said core array on a first individual bus line segment back into the core array on a second line segment, and

further comprising a plurality of repeatable interface circuits surrounding said core array each said repeatable interface circuit positioned between said plurality of I/O cells and said core array and functioning to programmably couple said line segments of said vertical and horizontal buses emerging from said core array to said I/O cells.

5. The field programmable gate array of claim 4 wherein each repeatable interface circuit has a substantially identical structure and includes a routing area comprised of a plurality of programmable connection matrices which are sparsely populated with programmable connection circuits and wherein every said programmable connection circuit is comprised of an active repeater, said programmable connection circuits located at selected intersections of individual signal lines, said programmable connection matrices being programmable to route signals on said line segments of said vertical and horizontal buses to specific ones of a plurality of inputs and outputs of said I/O cells.

6. A field programmable gate array comprising:

a core array of programmable logic blocks each having data inputs and data outputs which are programmably coupled through one or more programmable active repeaters to one or more selected individual signal lines of at least one of a plurality of vertical and horizontal buses,

said vertical and horizontal buses comprised of a plurality of individual conductive signal lines each of which are divided into segments by a plurality of active repeaters,

said vertical and horizontal buses intersecting at a plurality of intersections, each intersection being a programmable connection matrix which has a plurality of programmable connection circuits therein,

each said programmable connection circuit being an active repeater which is coupled to a power supply having high and low voltage supplies which are set at the voltage levels of logic 1 and logic 0, said active repeater functioning to programmably regenerate input signals on a preselected individual conductive signal line of said horizontal buses on one or more preselected individual conductive signal lines of said vertical buses or vice versa for either unidirectional or bidirectional communication by using a transistor amplifier and high impedance output stage such that, when the active repeater is enabled, it uses transistor action to gate current from said power supply into the line segment or input being driven in response to a transition to a particular logic state by said input signal and to gate current out of said line segment or input being driven into said power supply in response to a transition to a second binary logic state by said input signal,

said programmable logic blocks being coupled to each other through interconnections comprised of individual segments of said individual conductive signal lines of said vertical and horizontal buses and selected active repeaters which are programmed to be enabled so as to drive signals between the appropriate segments to make the necessary connections to implement a desired functionality for said field programmable gate array, and wherein each active repeater is optimally structured and sized in integrated circuit form to drive a known capacitive load to cause logic transitions at a desired speed.

7. The field programmable gate array of claim 6 further comprising a plurality of I/O cells surrounding said core array, each I/O cell being programmable as a data input or a data output or as both an input and an output, with the I/O cells programmed as both inputs and outputs functioning to return data emerging from said core array on a first line segment back into the core array on a second line segment, and a plurality of repeatable interface circuits surrounding said core array and adjacent said plurality of I/O cells said repeatable interface circuits functioning to programmably connect said line segments of said vertical and horizontal buses to said I/O cells to implement a desired functionality for said field programmable gate array, and wherein the different programmable connection matrices have a plurality of different patterns of programmable connection circuits at intersections between said conductors of said horizontal and vertical buses, with said different patterns of programmable connection circuits hereafter referred to as types, said different programmable connection matrices having a pattern of types of programmable connection matrices along the length of at least some buses with said pattern repeating in a periodic fashion, along said horizontal buses only.

8. The field programmable gate array of claim 7 wherein each repeatable interface circuit has an substantially identical structure and includes a routing area comprised of a plurality of programmable connection matrices each of which has a plurality of programmable connection circuits comprised of active repeaters at selected intersections of individual signal lines, said programmable connection matrices being programmable to route signals on said individual signal conductors of said vertical and horizontal bus signal lines to specific ones of said I/O cells.

9. The apparatus of claim 6 wherein each programmable connections matrix is sparsely populated with active repeaters which function to programmably couple preselected individual conductive signal lines of said horizontal buses to preselected individual conductive signal lines of said vertical buses, at least some of said programmable connection matrices having different connection possibilities than the others, but all programmable connection circuits in said programmable connection matrices are comprised of active repeaters, sparse population being defined as the presence of an active repeater only at some but not all the intersections of individual conductive signal lines within said horizontal and vertical buses, different connection possibilities being defined as different patterns of sparse population from one programmable connection matrix to the next.

10. A field programmable gate array apparatus having an array of programmable logic blocks and a plurality of I/O cells, and further comprising:

a plurality of horizontal and vertical buses each comprised of a plurality of data input and data output signal lines which are each segmented into a plurality of segments by active repeaters which can be programmed to be "on" or "off";

a plurality of active repeaters each having an enabled and disabled state and structured to selectively programmably couple predetermined individual conductors of said horizontal buses to predetermined individual conductors of said vertical buses at a plurality of locations in programmable connection matrices located at every intersection of a horizontal and vertical bus; and

a plurality of repeatable interface units coupling said I/O cells to said data input and data output signal lines through routing areas comprised of a plurality of O_-- lines and a plurality of I_-- lines and a plurality of active repeaters;

and wherein every point in said field programmable gate array where a programmable connection can be made is implemented with an active repeater which comprises at least one transistor amplifier having an output stage which is optimized in transistor size and current drive capability to drive a known, fixed load at a desired speed coupled to the output of said output stage and which presents a high impedance to said output when said active repeater is disabled, each said active repeater coupled to a power supply having high and low voltage rails supplying voltages at logic 1 and logic 0 levels, respectively, and each said active repeater having a gain of greater than one and structured to use transistor action to apply gain to input signals supplied to said active repeater to generate output signals at said output and to use transistor action to selectively couple either the current drive and current sink capacity of said power supply to selectively drive current into and sink current out of said load driven by said active repeater depending upon the state of said input signal, and wherein said active repeaters in adjacent lines of said horizontal and vertical buses are positionally staggered in echelon fashion, and wherein every said programmable connection matrix along the length of said horizontal buses has a different pattern of active repeaters than its immediately adjacent neighbors.

11. A field programmable gate array apparatus having an array of programmable logic blocks and a plurality of I/O cells, and further comprising:

a plurality of horizontal and vertical buses each comprised of a plurality of data input and data output signal lines which are each segmented into a plurality of segments by bidirectional active repeater means, each said bidirectional active repeater means coupled to an external power supply when said field programmable gate array is in operation and functioning to selectively, programmably regenerate digital signals received from one line segment on another line segment by applying gain to a signal propagating in one line segment so as to reconstruct said input signal as an output signal on an output line segment, and at least substantially preserve or speed up the rise and fall times of pulses in said input signal in the reconstructed output signal by using transistor action and the gain of said transistor to selectively gate current from said power supply into or out of parasitic capacitance loading said output segment in accordance with said input signal and at least some of said active repeater means functioning to perform these functions for signals propagating in either direction;

a plurality of active repeater means coupled to an external power supply when said field programmable gate array is operating, each for selectively programmably coupling predetermined individual conductors of said horizontal buses to predetermined individual conductors of said vertical buses at a plurality of locations and for applying transistor action to a signal propagating in one line segment coupled to an input of said active repeater so as to reconstruct said signal on an output line segment so as to selectively couple current drive or current sink capacity of said power supply to said output line segment in accordance with the state of said input signal so as to speed up the rise and fall times of the input signal in the reconstructed output signal; and

a plurality of repeatable interface units coupling said I/O cells to said data input and data output signal lines through routing areas comprised of a plurality of O_-- line segments and a plurality of I_-- line segments and a plurality of programmable connection matrices sparsely populated with active repeater means to a plurality of selected line segments of either said vertical or horizontal buses and a plurality of line segments going into and coming out of said I/O cells, each said active repeater means coupled to an external power supply when said active repeater is operating, for selectively, programmably receiving a signal propagating in one line segment and reconstructing said signal on an output line segment so as to speed up rise and fall times of the input signal in the reconstructed output signal by driving the parasitic capacitance load on said output line segment using transistor action to selectively couple either the current drive or current sink capacity of said power supply to said output line segment in accordance with the state of said input signal;

and wherein every location in said field programmable gate array where a programmable connection can be made is implemented with an active repeater.

12. The apparatus of claim 11 further comprising bidirectional active repeater means coupling both ends of all or a preselected number of said O_-- lines and said I_-- lines of each repeatable interface unit to the corresponding O_-- lines and I_-- lines of neighboring repeatable interface units, and wherein every active repeater means includes an output stage which is optimized in device size and current drive capacity to drive a known capacitive load at a desired speed.

13. A field programmable gate array having a plurality of programmable I/O cells and a plurality of programmable logic blocks and a plurality of data input and data output signal lines forming signal buses and which are programmably coupled to said logic blocks, characterized by

a plurality of repeatable interface means for coupling said I/O cells to said data input and data output signal lines of said signal buses through routing areas comprised of a plurality of O_-- line segments and a plurality of I_-- line segments and a plurality of active repeater means for programmably connecting data input and output lines from said signal buses to said O line segments and said I line segments:

and a plurality of line segments going into and coming out of said I/O cells

and a plurality of active repeater means used to implement every programmable connection in said field programmable gate array between said data input and data output lines of said signal buses and between input and output signal lines of said logic blocks and the data input and data output lines of said signal buses and between said lines segments goina into and coming out of said I/O cells and to segment the individual input and output signal lines of said buses, each said active repeater means for selectively, programmably receiving the digital signals propagating one one line segment coupled to an input of said active repeater means and regenerating said digital signal with faster rise and fall times on another line segment coupled to an output of said active repeater means by using gain and transistor action to selectively gate the current drive or current sink capacity of an external power supply to said output based upon the state of said input signal.

14. The apparatus of claim 13 further comprising a plurality of bidirectional active repeaters selectively, programmably coupling at least some of said O_-- line segments of at least some of said repeatable interface means to at least some of the O_-- line segments of one or more neighboring repeatable interface means, and further comprising a plurality of bidirectional active repeaters selectively, programmably coupling at least some of said I_-- line segments of at least some of said repeatable interface means to at least some of the I_-- line segments of one or more neighboring repeatable interface means, and wherein every active repeater means includes an output stage which is optimized in device size and current drive capacity to drive a known capacitive load at a desired speed.

15. A field programmable gate array having a plurality of programmable I/O cells and a plurality of programmable logic blocks and a plurality of data input and data output signal lines forming signal buses and and wherein said signal lines of said signal buses are programmably coupled to said logic blocks using active repeaters and wherein said buses intersect at partially populated programmable connection matrices, said field programmable gate array characterized by a plurality of unidirectional and bidirectional active repeaters at every location of a programmable connection in said field programmable gate array, each said active repeater programmable to have an enabled and a disabled state and comprising a transistor amplifier having larger than unity gain and an output stage which presents a high impedance to the output of said active repeater when said active repeater is disabled and coupled to an external power supply in such a way as to selectively, programmably regenerate digital signals propagating on one signal line on another signal line coupled to the output of said active repeater while speeding up the rise and fall times of said digital signal by using transistor action to selectively coupled either the current drive or current sink capacity of said external power supply to the output of said active repeater so as to charge or discharge the parasitic capacitance coupled to said output using said external power supply depending upon the state of the input signal thereby causing each active repeater to inherently limit the amount of parasitic capacitive load which loads a driver coupled to each line segment between active repeater boundaries to only the total parasitic capacitances actually directly connected to said line segment.

16. A connection network on an integrated circuit field programmable gate array, comprising:

a plurality of signal sources from which emanate digital signals having pulses that have rise and fall times;

a first plurality of signal line segments each of which has parasitic capacitance and resistance affecting digital signals propagating therein such that rise times and fall time of pulses of digital signals propagating along each said line segment are degraded by the combined RC time constant of said parasitic capacitance and resistance;

a second plurality of signal line segments each of which has parasitic capacitance and resistance affecting digital signals propagating therein such that rise times and fall time of pulses of digital signals propagating along each said line segment are degraded by the combined RC time constant of said parasitic capacitance and resistance;

high and low rail power supply conductors carrying voltages from an external power supply at logic 1 and logic 0 levels, respectively;

a plurality of inputs of logic blocks or of input/output circuit to which digital signals from said signal sources must be supplied each said input having at least parasitic capacitance and parasitic resistance affecting it and acting as at least part of the load of said input;

a plurality of programmable connection circuits with at least one said programmable connection circuit located at each programmable connection point in said connection network, each having an input and an output, and each for programmably connecting a signal source or one or more of said first or second plurality of line segments coupled to said input to one or more of said line segments in said first or second plurality of line segments or to one or more of said inputs of logic blocks coupled to said output;

and wherein each said programmable connection circuit has an enabled state and a disabled state and is comprised of;

a transistor amplifier coupled to said input and coupled to said high and low voltage rails and having an output stage, said transistor amplifier and output stage combining to use transistor action in response to the logic transitions of signals received at said input to selectively gate current from said high voltage rail into said output or gate current from said output into said low voltage rail depending upon the logic state of the input signal at said input when said transistor amplifier and output stage are enabled, and to present a high impedance to said output when said transistor amplifier and output stage are disabled; and

enabling circuitry coupled to said transistor amplifier and output stage to provide programmability of each said programmable connection circuit such that each said programmable connection circuit has at least an enabled state and a disabled state wherein a high impedance is presented to said output, and having a programming signal input for receiving an programming signal having at least enable and disable states which control whether said enabling circuitry enables or disables said transistor amplifier and said output stage.

17. The apparatus of claim 16 wherein said output stage of each said programmable connection circuit is optimized in terms of size and current drive capability so as to drive only the parasitic capacitance and parasitic resistance load of said output of said programmable connection circuit at the speed at which said field programmable gate array is designed to operate.

18. A programmable connection circuit for programmably connecting a line segment in a field programmable gate array to another line segment, comprising:

a high rail conductor of a power supply carrying a voltage equal to logic 1;

a low rail conductor of a power supply carrying a voltage equal to logic 0;

an input for receiving an input digital signal with a degraded rise time and a degraded fall time for every pulse from the rise time and fall time each pulse in said input digital signal originally had;

an output;

a constant current source;

a transistor amplifier comprising at least two transistors coupled as a differential pair between said high and low rail conductors of said power supply so as to share a constant current generated by said constant current source, and having an input coupled to said input so as to receive said digital input signal, for generating a digital signal at an output which replicates the logic transitions of said input digital signal received at said input but which has, for each pulse in said output signal corresponding to a pulse in said input signal, a regenerated rise time and regenerated fall time each of which is faster than said degraded rise time and fall time, respectively, of the corresponding pulse of said digital input signal;

at least one enabling transistor coupled to said constant current source and having an input for receiving a digital enable signal having first and second logic states, for enabling said constant current source in said first state of said enable signal and disabling said constant current source in said second state of said enable signal; and

at least one enabling transistor coupled to said at least two transistors coupled as a differential pair and having an input for receiving said enable signal, for enabling operation of said transistor amplifier to generate said output signal at said output of said transistor amplifier for said first state of said enable signal and for disabling generation of said output signal at said output of said transistor amplifier for said second state of said enable signal; and

an output stage means having an output coupled to said output of said active repeater and having an input coupled to said output of said transistor amplifier, for selectively coupling said output to said high rail voltage supply or said low rail voltage supply such that the parasitic capacitance of said load is charged or discharged by said external power supply by transistor action in accordance with the signal received from said transistor amplifier when said output stage means is programmed to be enabled, and to present a high impedance to said output when said output stage means is disabled.

19. An active repeater for use in coupling digital signals between segments of conductors in a field programmable gate array coupled to said active repeater, comprising:

a high rail conductor of a power supply;

a low rail conductor of a power supply;

an input for receiving an input digital signal with a degraded rise time and a degraded fall time for every pulse from the rise time and fall time each pulse in said input digital signal originally had;

an output;

a constant current source;

a transistor amplifier comprising at least two MOS transistors coupled as a differential pair between said high and low rail conductors of said power supply so as to share a constant current generated by said constant current source, and having an input coupled to receive said input digital signal, for generating a digital signal at said output which replicates the logic transitions of said input digital signal received at said input but which has, for each pulse in said output signal corresponding to a pulse in said input signal, a regenerated rise time and regenerated fall time each of which is faster than said degraded rise time and fall time of the corresponding pulse of said digital input signal;

at least one enabling MOS transistor coupled to said constant current source and having an input for receiving a digital enable signal having first and second logic states, for enabling said constant current source in said first state of said enable signal and disabling said constant current source in said second state of said enable signal; and

at least one enabling MOS transistor coupled to said at least two MOS transistors coupled as a differential pair and having an input for receiving said enable signal, for enabling operation of said differential pair to generate said output signal at said output for said first state of said enable signal and for disabling generation of said output signal at said output for said second state of said enable signal; and

an output stage means having an output coupled to said output of said active repeater and having an input coupled to said output of said transistor amplifier, for selectively coupling said output to said high rail voltage supply or said low rail voltage supply such that the parasitic capacitance of said load is charged or discharged by said external power supply by transistor action in accordance with the signal received from said transistor amplifier when said output stage means is programmed to be enabled, and to present a high impedance to said output when said output stage means is disabled.

20. An active repeater for use in coupling digital signals between segments of conductors in a field programmable gate array coupled to said active repeater, comprising:

a high rail conductor of a power supply;

a low rail conductor of a power supply;

an input for receiving an input digital signal with a degraded rise time and a degraded fall time for every pulse from the rise time and fall time each pulse in said input digital signal originally had;

an output;

a constant current source;

transistor amplifier means for receiving said digital input signal and for generating a digital signal at an output which replicates the logic transitions of said input digital signal received at said input but which has, for each pulse in said output signal corresponding to a pulse in said input signal, a regenerated rise time and regenerated fall time each of which is faster than said degraded rise time and fall time of the corresponding pulse of said digital input signal;

enabling means for selectively enabling said transistor amplifier means in accordance with the state of a programming signal; and

an output stage means coupled to said transistor amplifier means, for selectively coupling said output of said active repeater to said high rail voltage supply or said low rail voltage supply by transistor action in accordance with the signal received at said input of said active repeater when said output stage means is programmed to be enabled such that the parasitic capacitance of said load is charged or discharged by said external power supply, and to present a high impedance to said output when said output stage means is disabled.

21. A method of designing an interconnect structure for the core logic block array of an integrated field programmable gate array, comprising the steps:

laying out logic blocks having inputs and outputs;

laying out a plurality of rows and columns of buses with a plurality of individual conductors in each said bus, each said column and row of buses being routed so as to pass adjacent to a plurality of logic blocks;

laying out high and low voltage rail conductors which are to be coupled to an external power supply;

selecting a plurality of points where said bus conductors are to be programmably connected to each other and a plurality of points where inputs and outputs of said logic blocks are to be programmably connected to one or more individual conductors of said one or more of said buses;

at each said point, laying out a programmable connection circuit, each said programmable connection circuit comprising;

a transistor amplifier having an input coupled to an output of a logic block or a line segment comprising a portion of one of said plurality of individual conductors of one of said buses, and having an output stage having an output coupled to an input of a logic block or a line segment comprising a portion of one of said plurality of individual conductors of one of said buses, both said transistor amplifier and said output stage coupled to said high and low voltage rail conductors, each said transistor amplifier and output stage structured so as to use transistor action to selectively gate current from said high voltage rail into said line segment or logic block input coupled to said transistor amplifier output or gate current stored in the parasitic capacitances loading said line segment or logic block input coupled to said transistor amplifier output into said low voltage rail conductor depending upon the state of the input signal at said transistor amplifier input, and

enabling circuitry coupled to said transistor amplifier and output stage to provide programmability of each said programmable connection circuit such that each said programmable connection circuit has at least an enabled state and a disabled state wherein said input is isolated from said output.

22. A fast routing structure for a field programmable gate array having a plurality of logic blocks having inputs and outputs and a plurality of buses comprising a plurality of programmable connection circuits, wherein every programmable connection circuit has an input and an output and an enabled state and a disabled state, and wherein every programmable connection circuit is comprised of one or more transistor amplifiers and an output stage which presents a high impedance to said output when said programmable connection circuit is disabled, each programmable connection circuit coupled to high and low voltage ports of a power supply when the routing structure is in operation, each programmable connection circuit that is programmed to be enabled functioning to drive said output using transistor action to either gate current from said power supply into said output or to sink current out of said output to said low voltage port of said power supply depending upon the logic state of the signal at said input, each said programmable connection circuit also having an input receiving an enable signal the voltage of which defines whether said programmable connection circuit is enabled or disabled.

23. A routing structure for an integrated circuit field programmable gate array, comprising:

a plurality of buses each having a plurality of conductors which are segmented into two or more segments by one or more programmable unidirectional or bidirectional active repeaters, each active repeater coupled to high and low voltage terminals of an external power supply when in operation, and having an input coupled to one line segment and an output coupled to another line segment and comprising a transistor amplifier coupled to an output stage and an enabling circuit for enabling or disabling said active repeater in accordance with the state of a programming bit, each active repeater, when disabled, presenting a high impedance to said output, but when enabled, functioning to selectively couple the current drive capacity of said power supply into said output or sink current from said output through said active repeater into said external power supply using transistor action in response to the state of a signal at said input;

a plurality of logic blocks each having inputs and having outputs each of which is coupled to one or more programmable drivers, each said programmable driver having an output stage programmably coupled to one or more conductor segments of one or more of said buses, each output stage comprising one or more active repeaters;

and wherein each said output stage of a programmable driver or programmable active repeater is sized and structured so as to be optimized to drive only the load on the input or bus conductor segment to which it is connected to achieve a desired speed specification regardless of the state of programming of said programmable active repeaters and programmable drivers to implement a particular function for said field programmable gate array.

24. The apparatus of claim 23 wherein each said bus is comprised of a plurality of conductors and wherein each said conductor is segmented by one or more active repeaters throughout the length of said bus, and wherein said active repeaters are staggered in position such that the active repeaters that segment adjacent conductors of said bus are not all at the same relative location between the ends of said bus conductor although subgroups of active repeaters segmenting adjacent conductors can be next to each other so long as the active repeaters of every conductor in the bus are not immediately adjacent to each other.

25. In an integrated circuit field programmable gate array having an array of logic blocks with inputs and outputs programmably connected to the individual conductors of a plurality buses, a method of making propagation delays in said field programmable gate array easier to calculate for routing software, comprising:

segmenting said conductors in said buses with one or more active repeaters so as to divide each said conductor up into two or more segments which are programmably connected together by said active repeaters;

selectively coupling each said input and output of a logic block to a segment of a bus conductor via a programmable active repeater or a programmable driver, each said programmable driver having the same characteristics of an active repeater which has been programmed to be enabled of acting as a transistor amplifier coupled to an external power supply so as to use transistor action in response an input signal to create an output signal by selectively coupling the current drive or current sink capacity of said power supply to the line segment or logic block input coupled to the output of said driver or active repeater so as to drive current into or sink current out of the parasitic capacitance load to which said driver or active repeater is coupled such that said parasistic capacitance is not charged and discharged by the driver circuitry creating said input signals, but at least when disabled said active repeaters present a high impedance at their outputs, said transistor action and selective coupling of said power supply to said output driven by said active repeater inherently functioning to make the propagation delay of each line segment fixed by the parasitic resistance and capacitance of that line segment regardless of how many other line segments to which it is coupled thereby making delay calculations simple additions of the known delay of every line segment coupled together to make a connection.

26. The method of claim 25 further comprising the step of optimizing the output stage of each programmable active repeater transistor amplifier and programmable driver to drive just the known load of the line segment or logic block input to which it is connected at some desired speed thereby saving die area which can be used to layout more active repeaters thereby improving access and the number of programmable connection routes available to said routing software to implement a function.

27. The method of claim 26 wherein the step of segmenting said conductors of said buses is carried out by using a plurality of programmable bidirectional active repeaters in at least some of said conductors of each said bus such that said programmable bidirectional active repeaters can be programmed so that in at least some of said conductors of said buses different line segments of the same conductor may be programmed to be part of different conductive paths from a signal source to a circuit that needs the signal generated by said signal source thereby increasing the routing possibilities for said routing software.

28. The method of claim 26 wherein the step of segmenting said conductors of said buses is carried out by staggering the locations of active repeaters in adjacent conductors of the same bus in echelon fashion or some other fashion such that not all active repeaters in adjacent conductors of the bus are located immediately adjacent to each other so as to simplify the job of routing software that lays out a connection network for said field programmable gate array by increasing access.

29. The method of claim 28 wherein the step of segmenting said conductors of said buses is carried out by using a plurality of programmable bidirectional active repeaters in at least some of said conductors of each said bus such that said programmable bidirectional active repeaters can be programmed so that in at least some of said conductors of said buses different line segments of the same conductor may be programmed to be part of different conductive paths from a signal source to a circuit that needs the signal generated by said signal source thereby increasing the routing possibilities for said routing software.

30. The method of claim 25 wherein the step of segmenting said conductors of said buses is carried out by staggering the locations of active repeaters in adjacent conductors of the same bus in echelon fashion or some other fashion such that not all active repeaters in adjacent conductors of the bus are located immediately adjacent to each other so as to simplify the job of routing software that lays out a connection network for said field programmable gate array by increasing access.

31. The method of claim 30 wherein the step of segmenting said conductors of said buses is carried out by using a plurality of programmable bidirectional active repeaters in at least some of said conductors of each said bus such that said programmable bidirectional active repeaters can be programmed so that in at least some of said conductors of said buses different line segments of the same conductor may be programmed to be part of different conductive paths from a signal source to a circuit that needs the signal generated by said signal source thereby increasing the routing possibilities for said routing software.

32. The method of claim 25 wherein the step of segmenting said conductors of said buses is carried out by using a plurality of programmable bidirectional active repeaters in at least some of said conductors of each said bus such that said programmable bidirectional active repeaters can be programmed so that in at least some of said conductors of said buses different line segments of the same conductor may be programmed to be part of different conductive paths from a signal source to a circuit that needs the signal generated by said signal source thereby increasing the routing possibilities for said routing software.