Linear low noise phase-frequency detector

• US 6,002,273 A
• Filed: 10/05/1998
• Issued: 12/14/1999
• Est. Priority Date: 10/05/1998
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Humphreys, Scott Robert
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Luu, An T.
• Application Number:
  US09/166,756
• Time in Patent Office: 435 Days
• Field of Search: 327/3, 327/148, 327/157, 327/7, 327/12, 327/147, 327/156, 327/536, 327/63, 327/77, 327/78, 331/25, 363/59, 363/60
• US Class Current: 327/3
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

A phase-frequency detector (110) includes an output stage (300) and a control stage (200). The output stage includes a pump up switched current source (350), a pump down switched current sink (360), and a constant current source (325) that are coupled to a charge pump output node (111). The control stage generates, in response to a divided variable frequency signal (FV) (136) and a reference frequency signal (FR) (106), a pump up control signal (246) and a pump down control signal (216).

Claims

1. A phase-frequency detector, comprising:

an output stage; and

a control stage coupled to the output stage that generates, in response to a divided variable frequency signal (FV) and a reference frequency signal (FR), a pump up control signal and a pump down control signal,

wherein when FV lags FR by a lag time, the control stage generates the pump up control signal having the active state with a duration that is essentially equal to the lag time, and generates the pump down control signal having the active state with a duration that is essentially equal to a predetermined duration, and

wherein when FV leads FR by a lead time, the control stage generates the pump up control signal having a constant inactive state, and generates the pump down control signal having the active state that is equal to the predetermined duration plus the lead time.

2. The phase-frequency detector according to claim 1, wherein the control stage comprises:

a first flip-flop, having a clock input coupled to FR, wherein the first flip-flop generates a pump up internal signal that is set to the active state in response to an edge of FR;

a second flip-flop, having a clock input coupled to FV, wherein the second flip-flop generates the pump down control signal that is set to the active state in response to an edge of FV; and

an inhibit gate element, coupled to the pump up internal signal and the pump down control signal, that generates the pump up control signal.

3. The phase-frequency detector according to claim 2, wherein the inhibit gate element comprises:

an AND gate having the pump up internal signal as a first input; and

an inverter having the pump down control signal as an input, an output of which is coupled to a second input of the AND gate,

wherein the pump up control signal is generated at the output of the AND gate.

4. The phase-frequency detector according to claim 2, wherein the control stage comprises:

an AND gate that has the pump up internal signal and pump down control signal coupled thereto as inputs; and

wherein the first flip-flop has a first reset input that is coupled to the output of the AND gate, and

wherein the second flip-flop has a second reset input that is coupled to an output of the delay element.

5. The phase-frequency detector according to claim 4, wherein the control stage further comprises:

a delay element that has an input coupled to an output of the AND gate.

6. The phase-frequency detector according to claim 1, wherein the phase-frequency detector is implemented in one integrated circuit.

7. The phase-frequency detector according to claim 1, comprising a pump up switched current source coupled to a charge pump output node that sources a first current, I1, in response to a pump up control signal, a pump down switched current sink coupled to the charge pump output node that sources a second current, I2, in response to a pump down control signal, and a constant current source continuously sourcing a third current, I3, at the charge pump output node.

8. The phase-frequency detector according to claim 7, wherein I1 is substantially equal to I2 and a ratio of I3 to the I2 is approximately 1:

50.

9. The phase-frequency detector according to claim 7, wherein I1 is substantially equal to I2 and a ratio of I3 to I2 is greater than a ratio of the predetermined duration to a period of the reference frequency signal, FR.

10. An electronic equipment, comprising a phase-frequency detector that comprises:

an output stage; and

a control stage coupled to the output stage that generates, in response to a divided variable frequency signal (FV) and a reference frequency signal (FR), a pump up control signal and a pump down control signal,

wherein when FV lags FR by a lag time, the control stage generates the pump up control signal having the active state with a duration that is essentially equal to the lag time, and generates the pump down control signal having the active state with a duration that is essentially equal to a predetermined duration, and

wherein when FV leads FR by a lead time, the control stage generates the pump up control signal having a constant inactive state, and generates the pump down control signal having the active state that is egual to the predetermined duration plus the lead time.

11. An electronic equipment, comprising a phase-frequency detector that comprises:

an output stage comprising

a pump up switched current source coupled to a charge pump output node that sources a first current, I1, in response to a pump up control signal,

a pump down switched current sink coupled to the charge pump output node that sources a second current, I2, in response to a pump down control signal, and

a constant current source continuously sourcing a third current, I3, at the charge pump output node; and

a control stage coupled to the output stage that generates, in response to a divided variable frequency signal (FV) and a reference frequency signal (FR), a pump up control signal and a pump down control signal,

wherein when FV leads FR the control stage inhibits the pump up signal.

12. A phase-frequency detector, comprising:

an output stage comprising

a pump up switched current source coupled to a charge pump output node that sources a first current, I1, in response to a pump up control signal,

a pump down switched current sink coupled to the charge pump output node that sources a second current, I2, in response to a pump down control signal, and

a constant current source continuously sourcing a third current, I3, at the charge pump output node; and

a control stage coupled to the output stage that generates, in response to a divided variable frequency signal (FV) and a reference frequency signal (FR), a pump up control signal and a pump down control signal,

wherein when FV leads FR the control stage inhibits the pump up signal.

13. The phase-frequency detector according to claim 12,

wherein when FV lags FR by a lag time, the control stage generates the pump up control signal having an active state with a duration that is essentially equal to the lag time, and generates the pump down control signal having the active state with a duration that is essentially equal to a predetermined duration, and

wherein when FV leads FR by a lead time, the control stage generates the pump down control signal having the active state that is equal to the predetermined duration plus the lead time.

14. The phase-frequency detector according to claim 12, wherein I1 is substantially equal to I2 and the control stage generates the pump up control signal and pump down control signal such that a constant time offset that occurs during phase lock is determined by a product of a period of the reference frequency signal and a ratio of I3 to I2.

15. The phase-frequency detector according to claim 12, wherein I1 is substantially equal to I2 and a ratio of I3 to I2 is approximately 1:

50.

16. The phase-frequency detector according to claim 12, wherein the phase-frequency detector is implemented in one integrated circuit.