Digital filter

• US 6,002,297 A
• Filed: 01/29/1998
• Issued: 12/14/1999
• Est. Priority Date: 08/02/1995
• Status: Expired due to Fees

• Current Assignee: BTG International Limited (Boston Scientific Corporation)
• Original Assignee: British Technology Group Inter-Corporate Licensing Limited (Invesco Limited)
• Inventors: Scheelen, Jos
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US09/015,304
• Time in Patent Office: 684 Days
• Field of Search: 322/39, 322/40, 322/552, 322/559, 322/47, 322/556, 364/724.16, 375/350
• US Class Current: 327/556
• CPC Class Codes: G01S 13/758 using a signal generator powered by the interrogation signal
• CPC Class Codes: G06K 7/082 using inductive or magnetic sensors

Abstract

In a bandpass filter, a first cyclical analogue signal V3 at a center frequency divided by integer N in divide 44 and the divided signal supplied to a digital filter 48 as its system clock; a second cyclical analogue signal at a frequency, to be measured, differing by a small amount from the center frequency, is delayed by N cycles by a dynamic store 54; a substractor 56 subtracts the second signal from the delayed second signal and supplies any difference to the digital filter 48; the output of the digital filter is related to the frequency of the second signal, but the center frequency is suppressed. The filter may be used in an interrogation for an electronic detection system in which an interrogation signal is modified in frequency by a small amount, characteristic of a device to be detected.

Claims

1. A frequency detection circuit comprising:

a first node to receive a first cyclical analogue signal at a first frequency (f₁);

frequency converter means to receive the first cyclical analogue signal, to convert the first signal to a converted frequency signal, and to supply the converted frequency signal to a digital filter (48) as a system clock signal for said filter;

a second node to receive a second cyclical analogue signal at a second frequency (f₂) which differs from the first frequency by a small amount;

a delay circuit to delay the second signal by N cycles; and

a subtractor to receive a current value of the second cyclical analogue signal (S_c) from the second node and a delayed value of the second cyclical analog signal (S_p) from the delay circuit, to subtract them and to provide any difference to the digital filter as a difference signal, whereby the digital filter provides an output signal comprising the second frequency (f₂) and substantially suppressing any signal at the first frequency (f₁).

2. A detection circuit according to claim 1 in which the delay circuit comprises a dynamic storage unit.

3. A detection circuit according to claim 1 wherein N is 20.

4. A circuit according to claim 2 wherein N is 20.

5. An interrogator for an electronic detection system characterised by comprising:

a first oscillator arranged to transmit a first signal at a first frequency;

antenna means to receive a second signal at a second frequency differing by a small amount from the first frequency;

delaying means to delay the second signal by N cycles where N is an integer;

subtraction means to receive from the antenna means the second signal and from the delay means a delay of the second signal, to subtract the received second signal and the delayed second signal, and to provide any difference therebetween as a difference signal to a digital filter;

frequency converter means to convert the first frequency into a converted frequency signal and to supply the converted frequency signal to the digital filter as a system clock for said filter;

whereby the output of the digital filter identifies a presence of the second signal at the second frequency and substantially suppresses any signal at the first frequency.

6. An interrogator according to claim 5 wherein the means to divide comprises a phase-locked loop comprising a phase discriminator coupled to the first oscillator, a voltage controlled oscillator and a divider unit.

7. A circuit for interrogating an input signal at a second frequency originating as a result of an interrogation signal at a first frequency differing from the second frequency by a small amount, comprising:

a transmitter to emit the interrogation signal at the first frequency,

a receiver to receive the input signal at the second frequency,

a phase lock loop converting said input signal into an oscillation signal at a third frequency,

a node to receive a digitized version of the input signal from the receiver,

a delaying circuit to receive from the node the digitized version of the input signal and to output a delayed input signal equal to the digitized version of the input signal delayed by N cycles,

a subtractor having two inputs to receive, respectively, the digitized version of the input signal and the delayed input signal, to subtract them, and to output a resultant difference signal, and

a digital filter receiving the difference signal and said oscillation signal and producing an output signal comprising the second frequency (f₂) and substantially suppressing any signal at the first frequency (f₁).