Solid-state imaging apparatus

• US 6,002,435 A
• Filed: 04/01/1997
• Issued: 12/14/1999
• Est. Priority Date: 04/01/1996
• Status: Expired due to Term

• Current Assignee: Hamamatsu Photonics KK
• Original Assignee: Hamamatsu Photonics KK
• Inventors: Yamamoto, Hiroo, Mizuno, Seiichiro
• Primary Examiner(s): Garber, Wendy
• Assistant Examiner(s): NGUYEN, LUONG TRUNG
• Application Number:
  US08/831,713
• Time in Patent Office: 987 Days
• Field of Search: 348/241, 348/242, 348/248, 348/307, 348/308, 348/243, 358/463
• US Class Current: 348/307
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

In the solid-state imaging apparatus of the present invention, when a signal is output from the capacity element to the data signal output circuit, the voltage of the output terminal of the capacity element is kept at that attained when the switch was previously opened, namely, the initial voltage of the input terminal of the data signal output circuit, whereby the voltage of the input terminal of the data signal output circuit is stable without fluctuation. Therefore, no noise is generated in the output signal at the instant when the capacity element and data signal output circuit are short-circuited, whereby optical images can be captured with a high accuracy in a high speed.

Claims

1. A solid-state imaging apparatus for capturing a one-dimensional optical image, said apparatus comprising:

a line type photosensitive section comprising a plurality of photosensitive pixels, said photosensitive pixels being arranged along a predetermined direction, each of said photosensitive pixels converting an input light signal into a current signal and outputting the current signal;

integrating circuits arranged for said photosensitive pixels respectively, each of said integrating circuits selectively performing an integrating operation for the current signal output from the corresponding photosensitive pixel and an initial voltage level setting operation for an output signal;

clamping circuits arranged for said integrating circuit respectively, each of the clamping circuits selectively performing a clamping processing for a signal output from the corresponding integrating circuit and an initial voltage level setting operation for an output signal;

sample-and-hold circuits arranged for said clamping circuits respectively, each of said sample-and-hold circuits selectively performing a sampling and holding operation for a signal output from the corresponding clamping circuit;

first capacity elements arranged for said sample-and-hold circuits respectively, each of said first capacity elements outputting an AC component based on a signal output from the corresponding sample-and-hold circuit;

first switches arranged for said first capacity elements respectively, each of said first switches controlling an output of said first capacity element;

a data signal output circuit for performing an output operation of an output data signal based on a signal input from one of said first switches and setting an initial-voltage setting operation for an input terminal selectively; and

a timing control section for controlling operation timings of said plurality of photosensitive pixels, said integrating circuits, said clamping circuits, said sample-and-hold circuits, said first switches, and said data signal output circuit,

wherein said timing control section instructs;

said integrating circuits and said clamping circuits to perform the initial voltage level setting operation about the output terminals of said integrating circuits before the current signals are read out from said plurality of photosensitive pixels;

said first switches and said data signal output circuit to perform the initial voltage level setting operation about the output terminals of said first capacity elements and the input terminals of said data signal output circuit over a period extending from a time before the current signals are read out from the plurality of photosensitive pixels till a time at which said signal is being read out;

said integrating circuits to perform the integrating operation;

said clamping circuits to perform the clamping processing;

said sample-and-hold circuits to perform the sampling operation during a period in which the current signal is being read out from said plurality of photosensitive pixels; and

said clamping circuits to perform the initial voltage level setting operation, said sample-and-hold circuits to perform the sampling operation, said first capacity element to perform the output operation, and said data signal output circuit to perform the output operation during a period in which a signal is read out from said first capacity element after the current signals are read out from said plurality of photosensitive pixels.

2. An apparatus according to claim 1, wherein said data signal output circuit comprises:

an amplifier for amplifying a signal input from said first capacity element;

a second capacity element having a first terminal connected to an input terminal of said amplifier and a second terminal connected to an output terminal of said amplifier; and

a second switch having a first terminal connected to an input terminal of said amplifier and a second terminal connected to an output terminal of said amplifier, said second switch performing opening and closing operations in response to an initial voltage setting instruction signal input from said timing control section.

3. An apparatus according to claim 2, wherein said data signal output circuit further comprises:

a third switch having a first terminal connected to a first terminal of said second capacity element and a second terminal connected to a predetermined reference voltage source, said third switch performing, in response to said initial voltage setting instruction signal, opening and closing operations identical to those of said second switch; and

a fourth switch having a first terminal connected to a second terminal of said second capacity element and a second terminal connected to a predetermined reference voltage source, said fourth switch performing, in response to said initial voltage setting instruction signal, opening and closing operations identical to those of said second switch and third switch.

4. An apparatus according to claim 1, wherein each of said plurality of photosensitive pixels comprises:

a photodiode for converting said input light signal into a current signal; and

a second switch having a first terminal connected to an output terminal of said photodiode and a second terminal connected to a common signal line in said line type photosensitive section, said second switch performing opening and closing operations in response to one input signal among a plurality of scanning signals output from said timing control section.

5. An apparatus according to claim 1, wherein said integrating circuit comprises:

an amplifier for amplifying a signal output from the corresponding photosensitive pixel;

a second capacity element having a first terminal connected to an input terminal of said amplifier and a second terminal connected to an output terminal of said amplifier; and

a second switch having a first terminal connected to the input terminal of said amplifier and a second terminal connected to the output terminal of said amplifier, said second switch performing opening and closing operations in response to a reset instruction signal output from said timing control section.

6. An apparatus according to claim 1, wherein said clamping circuit comprises:

a second capacity element having an input terminal connected to an output terminal of the corresponding integrating circuit;

an amplifier having an input terminal connected to an output terminal of said second capacity element, said amplifier amplifying a signal input from said second capacity element;

a third capacity element having a first terminal connected to an input terminal of said amplifier and a second terminal connected to an output terminal of said amplifier; and

a second switch having a first terminal connected to the input terminal of said amplifier and a second terminal connected to the output terminal of said amplifier, said second switch performing opening and closing operations in response to a corresponding clamp instruction signal output from said timing control section.

7. An apparatus according to claim 1, wherein said sample-and-hold circuit comprises:

a second switch having a first terminal connected to an output terminal of the corresponding clamping circuit, said second switch performing opening and closing operations in response to a corresponding sample instruction signal output from said timing control section;

a second capacity element having a first terminal connected to a second terminal of said second switch and a second terminal connected to a predetermined voltage source; and

a buffer amplifier having an input terminal connected to the second terminal of said second switch, said buffer amplifier subjecting a signal output from said second switch to an impedance conversion.

8. An apparatus according to claim 1, wherein said first capacity element has an input terminal connected to an output terminal of the corresponding sample-and-hold circuit and an input terminal of said first switch, and said first switch has an output terminal connected to the input terminal of said data signal output circuit, and performs opening and closing operations in response to a corresponding scanning signal output from said timing control section.

9. An apparatus according to claim 1, wherein said timing control section outputs:

a read out signal for instructing said plurality of photosensitive pixels to output the current signals,

a reset instruction signal for instructing said integrating circuits to selectively perform the integrating operation and the initial voltage level setting operation,

clamp instruction signals for instructing said clamping circuits to selectively perform the clamping processing and the initial voltage level setting operation,

sample instruction signals for instructing said sample-and-hold circuits to selectively perform the sampling and holding operations,

scanning signals for instructing said first switches to selectively control the output of said first capacity elements and set the initial voltage of said first capacity elements, and

an initial voltage setting instruction signal for instructing said data signal output circuit to selectively perform the output operation and the initial voltage setting operation.

10. An apparatus according to claim 9, wherein said timing control section computes:

a logical sum of an all line selecting instruction signal for setting all of said line type photosensitive pixels to objects to be selected and a plurality of individual line selection instruction signals for respectively setting said line type photosensitive pixels to objects to be selected, so as to generate said scanning signals;

a logical sum of a result obtained when a logical product of individual clamp instruction signals for respectively setting said clamping circuits to objects to be selected and said scanning signals is computed and an all clamp instruction signal for setting all of said clamping circuits to objects to be selected, so as to generate said clamp instruction signals; and

a logical sum of a result obtained when a logical product of individual sample instruction signals for respectively setting said sample-and-hold circuits to objects to be selected and said scanning signals is computed and an all sample instruction signal for setting all of said sample-and-hold circuits to objects to be selected, so as to generate said sample instruction signals, and

wherein said timing control section sets;

said reset instruction signal and clamp instruction signals to logical true levels before the read out signal is set to a logical true level;

all of said scanning signals and initial voltage level setting instruction signal to logical true levels during a period extending from a time the read out signal is set to a logical true level till a time at which said signal is at the logical true level;

all of said sample instructions signal to a logical true level while said reset instruction signal is kept at a logical false level during a period in which the read out signal is at the logical true level; and

one of said clamp instruction signals corresponding to one signal selected from said scanning signals and one of sample instruction signals corresponding to one signal selected from said scanning signals to logical true levels during a period in which said scanning signal is set to the logical true level again after the read out signal is reset to the logical false level again.

11. A solid-state imaging apparatus for capturing a two-dimensional optical image, said apparatus comprising:

an area type photosensitive section having a first number of line type photosensitive sections arranged along a first direction and common signal lines arranged for said line type photosensitive sections, each of said line type photosensitive sections having a second number of photosensitive pixels arranged along a second direction, each of said photosensitive pixels converting an input light signal into a current signal, each of said photosensitive pixels in said line type photosensitive sections outputting the current signal to the corresponding common signal line;

integrating circuits arranged for said line type photosensitive sections respectively, each of said integrating circuits selectively performing an integrating operation for a signal output from the corresponding line type photosensitive section and an initial voltage level setting operation for an output signal;

clamping circuits arranged for said integrating circuits respectively, each of said clamping circuits selectively performing a clamping processing for a signal output from the corresponding integrating circuit and an initial voltage level setting operation for an output signal;

sample-and-hold circuits arranged for said clamping circuits respectively, each of sample-and-hold circuits selectively performing sampling and holding operations for a signal output from the corresponding clamping circuit;

first capacity elements arranged for said sample-and-hold circuits respectively, each of first capacity elements performing an output processing of an AC component based on a signal output from the corresponding sample-and-hold circuit;

first switches arranged for said first capacity elements respectivly, each of said switches controlling an output of the corresponding first capacity element;

a data signal output circuit for selectively performing an output processing of respective output data signal based on a signal output from one of said first switches and an initial-voltage setting operation for an input terminal; and

a timing control section for controlling operation timings of said photosensitive pixels, said integrating circuits, said clamping circuits, said sample-and-hold circuits, said first switches, and said data signal output circuit,

wherein said timing control section instructs;

said integrating circuits and clamping circuits to perform the initial voltage level setting operation before a signal is read out from one photosensitive pixel selected from said photosensitive pixels in each of said line type photosensitive sections;

said first switches and said data signal output circuit to perform the initial voltage setting operation about the output terminals of said first capacity elements and the input terminal of said data signal output circuit over a period extending from a time before the signal is read out from one photosensitive pixel selected from the photosensitive pixels in each of said line type photosensitive sections till a time at which said signal is being read out;

said integrating circuits to perform the integrating operation;

said clamping circuits to perform the clamping processing;

said sample-and-hold circuits to perform the sampling operation during a period in which the signal is being read out from one photosensitive pixel selected from the photosensitive pixels in each of said line type photosensitive sections;

said data signal output circuit to perform the initial voltage setting operation about the input terminal of said data signal output circuit during a period in which a signal is being read out from one of said first capacity elements corresponding to one line type photosensitive section selected from said line type photosensitive sections after the signal is read out from one photosensitive pixel selected from the line type photosensitive pixels in each of said line type photosensitive sections; and

one of said clamping circuits corresponding to one line type photosensitive section selected from said line type photosensitive sections to perform the initial voltage level setting operation;

one of said sample-and-hold circuits corresponding to one line type photosensitive section selected from said line type photosensitive sections to perform the sampling operation;

one of said first capacity elements corresponding to one line type photosensitive section selected from said line type receiving sections to perform the output processing; and

said data signal output circuit to perform the output processing.

12. An apparatus according to claim 11, wherein said data signal output circuit comprises:

an amplifier for amplifying each signal input from said plurality of first capacity elements;

a second capacity element having a first terminal connected to an input terminal of said amplifier and a second terminal connected to an output terminal of said amplifier; and

a second switch having a first terminal connected to the input terminal of said amplifier and a second terminal connected to the output terminal of said amplifier, said second switch performing opening and closing operations in response to an initial voltage setting operation signal input from said timing control section.

13. An apparatus according to claim 12, wherein said data signal output circuit further comprises:

a third switch having a first terminal connected to a first terminal of said second capacity element and a second terminal connected to a predetermined reference voltage source, said third switch performing, in response to said initial voltage setting operation signal, opening and closing operations identical to those of said second switch; and

a fourth switch having a first terminal connected to a second terminal of said second capacity element and a second terminal connected to a predetermined reference voltage source, the fourth switch performing, in response to said initial voltage setting operation signal, opening and closing operations identical to those of said second switch and third switch.

14. An apparatus according to claim 11, wherein each of said photosensitive pixels comprises:

a photodiode for converting said input light signal into a current signal; and

a second switch having a first terminal connected to an output terminal of said photodiode and a second terminal connected to one of a plurality of common signal lines in said number of line type photosensitive sections, said second switch performing opening and closing operations in response to one input signal among a plurality of first scanning signals output from said timing control section.

15. An apparatus according to claim 11, wherein each of said integrating circuits comprises:

an amplifier for amplifying a signal output from the corresponding line type photosensitive section;

a second capacity element having a first terminal connected to an input terminal of said amplifier and a second terminal connected to an output terminal of said amplifier; and

a second switch having a first terminal connected to the input terminal of said amplifier and a second terminal connected to the output terminal of said amplifier, said second switch performing opening and closing operations in response to a reset instruction signal output from said timing control section.

16. An apparatus according to claim 11, wherein each of said clamping circuits comprises:

a second capacity element having an input terminal connected to an output terminal of the corresponding integrating circuit;

an amplifier having an input terminal connected to an output terminal of said second capacity element and amplifies a signal output from said second capacity element;

a third capacity element having a first terminal connected to the input terminal of said amplifier and a second terminal connected to an output terminal of said amplifier; and

a second switch having a first terminal connected to the input terminal of said amplifier and a second terminal connected to the output terminal of said amplifier, said second switch performing opening and closing operations in response to one input clamp instruction signal among a clamp instruction signals output from said timing control section.

17. An apparatus according to claim 11, wherein each of said sample-and-hold circuits comprises:

a second switch having a first terminal connected to an output terminal of the corresponding clamping circuit, said second switching opening and closing operations in response to one input sample instruction signal among a plurality of sample instruction signals output from said timing control section;

a second capacity element having a first terminal connected to a second terminal of said second switch and a second terminal connected to a predetermined voltage source; and

a buffer amplifier having an input terminal connected to the second terminal of said second switch, said buffer amplifier subjecting a signal input from said second switch to an impedance conversion.

18. An apparatus according to claim 11, wherein each of said first capacity elements has an input terminal connected to an output terminal of the corresponding said sample-and-hold circuit and an output terminal connected to an input terminal of the corresponding first switch, and each of said first switches has an output terminal connected to the input terminal of said data signal output circuit, said first switch performing opening and closing operations in response to one input signal among a plurality of second scanning signals output from said timing control section.

19. An apparatus according to claim 11, wherein said timing control section outputs:

first scanning signals for individually instructing said photosensitive pixels to perform the output processing which is common among said line type photosensitive sections,

a reset instruction signal for instructing said integrating circuits to selectively perform the integrating operation and the initial voltage level setting operation;

a plurality of clamp instruction signals for individually instructing said clamping circuits to selectively perform the clamping processing and the initial voltage level setting operation;

sample instruction signals for individually instructing said sample-and-hold circuits to selectively perform sampling and holding operations,

second scanning signals for individually instructing said first switches to selectively control the outputs of said first capacity elements and set the initial voltage level of first capacity elements, and

an initial voltage setting instruction signal for instructing said data signal output circuit to selectively perform the output operation and the initial voltage setting operation.

20. An apparatus according to claim 19, wherein said timing control section computes:

a logical sum of an all line selecting instruction signal for setting all of said line type photosensitive sections to objects to be selected and a plurality of individual line selection instruction signals for respectively setting said line type photosensitive sections to objects to be selected, so as to generate said second scanning signals;

a logical sum of a result obtained when a logical product of individual clamp instruction signals for respectively setting said clamping circuits to objects to be selected and said second scanning signals is computed and an all clamp instruction signal for setting all of said clamping circuits to objects to be selected, so as to generate said clamp instruction signals; and

a logical sum of a result obtained when a logical product of individual sample instruction signals for respectively setting said sample-and-hold circuits to objects to be selected and said second scanning signals is computed and an all sample instruction signal for setting all of said sample-and-hold circuits to objects to be selected, so as to generate said sample instruction signals, and

wherein said timing control section sets;

said reset instruction signal and all of said clamp instruction signals to logical true levels before one signal selected from said first scanning signals is set to a logical true level;

all of said second scanning signals and said initial potential setting instruction signal to logical true levels during a period extending from a time before one signal selected from said first scanning signals is set to a logical true level till a time at which said signal is at the logical true level;

all of said sample instruction signals to logical true levels while said reset instruction signal is kept at a logical false level during a period in which one signal selected from said first scanning signals is at the logical true level;

said initial potential setting instruction signal to a logical true level during a period in which one of said second scanning signals is reset to the logical true level after one signal selected from said first scanning signals is reset to the logical false level; and

one of said clamp instruction signals corresponding to one signal selected from said second scanning signals and one of said sample instruction signals corresponding to one signal selected from said second scanning signals to logical true levels.