Method and apparatus for reducing flickers in video signal conversions
First Claim
1. A method for reducing flickers in transforming non-interlaced video signals to interlaced video signals, each of the video signals comprising a plurality of lines of signals, each of the line signal comprising pixels, the method comprising the steps of:
- (a) receiving the pixel image in a memory;
(b) outputting the pixels successively and line by line;
(c) shifting the pixels received from step (b) into a first FIFO line buffer;
(d) receiving a kth pixel of a (n+1 )th line signal from the first FIFO line buffer as a reference pixel;
(e) receiving a kth pixel of the nth line from step (b) as a determining pixel;
(f) comparing the reference pixel with the determining pixel;
(g) detecting a first dissimilarity value between the reference pixel and the determining pixel in accordance with the comparison in step (f);
(h) employing a first adjustable factor;
(i) adjusting the first dissimilarity value with the first adjustable factor;
(j) adding the adjusted first dissimilarity value obtained in step (i) to the determining pixel; and
(k) outputting a first new determining pixel resulting from step (j).
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Abstract
The present invention discloses a system for adaptively reducing flickers in converting non-interlaced video signals to interlaced video signals. To preserve the original image quality in the non-interlaced video signals, the disclosed system examines the pixel values in at least two adjacent lines to decide if a reduction process should be turned on. If there is a need, the reduction process further examines the difference in the pixels from the adjacent lines to determine how to adjust a corresponding output to eliminate flickers in the resultant converted video signals. The adjusting means is based on an adjusting factor or the calculated difference between pixels which is further used in a function to eventually produce a converted interlaced signal with minimum visual errors.
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Citations
16 Claims
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1. A method for reducing flickers in transforming non-interlaced video signals to interlaced video signals, each of the video signals comprising a plurality of lines of signals, each of the line signal comprising pixels, the method comprising the steps of:
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(a) receiving the pixel image in a memory; (b) outputting the pixels successively and line by line; (c) shifting the pixels received from step (b) into a first FIFO line buffer; (d) receiving a kth pixel of a (n+1 )th line signal from the first FIFO line buffer as a reference pixel; (e) receiving a kth pixel of the nth line from step (b) as a determining pixel; (f) comparing the reference pixel with the determining pixel; (g) detecting a first dissimilarity value between the reference pixel and the determining pixel in accordance with the comparison in step (f); (h) employing a first adjustable factor; (i) adjusting the first dissimilarity value with the first adjustable factor; (j) adding the adjusted first dissimilarity value obtained in step (i) to the determining pixel; and (k) outputting a first new determining pixel resulting from step (j). - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for reducing flickers in transforming non-interlaced video signals to interlaced video signals, each of the video signals comprising a plurality of lines of signals, each of the line signal comprising pixels, the method comprising the steps of:
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(a) receiving the pixel image in a memory; (b) outputting the pixels successively and line by line; (c) shifting the pixels received from step (b) successively into 2N line buffers, each of the 2N line buffers having an input and an output and being connected in series, each of the 2N buffers being defined as ith line buffer, where i is defined in a range from 1 to N, and each of the 2N buffers receiving the pixels shifted out from a predecessor thereof; (d) receiving a kth pixel of a nth line, as a current pixel, from the Nth line buffers in accordance with step (c); (e) receiving a kth pixel of a (n+1)th line, as an advancing pixel, from the (N+i)th line buffer in accordance with step (c); (f) receiving a kth pixel of a (n-1)th line, as a previous pixel, from the (N-i)th line buffer in accordance with step (c); (g) comparing the previous pixel with the current pixel; (h) comparing the current pixel with the next pixel; (i) detecting a first dissimilarity value between the previous pixel and the current pixel in accordance with the comparison in step (g); (j) detecting a second dissimilarity value between the current pixel and the next pixel in accordance with the comparison in step (i); (k) employing a first adjustable factor, wherein the first adjustable factor is a first function of the first dissimilarity value; (l) employing a second adjustable factor, wherein the second adjustable factor is a second function of the second dissimilarity value; (m) adjusting the first dissimilarity value with the first adjustable factor; (n) adjusting the second dissimilarity value with the second adjustable factor; (o) repeating step (d) to (n) N times, thereby there N pairs of the first and second dissimilarity values are generated; (p) summarizing the adjusted first dissimilarity values and the adjusted second dissimilarity values obtained in step (o) and the pixel received from the Nth buffer line; and (q) outputting a new kth pixel resulting from step (p). - View Dependent Claims (9, 10)
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11. An apparatus for reducing flickers in transforming non-interlaced video signals to interlaced video signals, each of the video signals comprising a plurality of lines of signals, each of the line signal comprising pixels, the apparatus comprising:
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a first line buffer and a second line buffer coupled in series, the first line buffer receiving the non-interlaced video signals comprising lines of signals;
each of the signals comprising N pixels, the first and the second line buffers each comprising N memory cells, each of the memory cells for one of the pixels, such that the first line buffer outputs one-line delayed non-interlaced video signals and the second line buffer outputs two-line delayed non-interlaced video signals;a first and a second comparing circuits, each having a first input and a second input, the first and the second inputs of the first comparing circuit receiving the non-interlaced video signals and the one-line delayed non-interlaced video signals from the first line buffer, the first comparing circuit outputting a first similarity value by comparing two kth pixels, respectively, in the non-interlaced video signals and the one-line delayed non-interlaced video signals, the first and the second inputs of the second comparing circuit receiving the one-line non-interlaced video signals from the first line buffer and the two-line delayed non-interlaced video signals from the second line buffer, the second comparing circuit outputting a second similarity value by comparing two kth pixels, respectively in the one-line non-interlaced video signals and the two-line delayed non-interlaced video signals; and a first and second multiplying circuits, each respectively coupled to the first and second comparing circuits, multiplying, respectively, the first similarity value by a first adjustable factor to produce an adjusted first similarity value and the second similarity value by a second adjustable factor to produce an adjusted second similarity value. - View Dependent Claims (12, 13, 14, 15, 16)
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Specification