Read-only-memory (ROM) having a memory cell that stores a plurality of bits of information

• US 6,002,607 A
• Filed: 02/24/1998
• Issued: 12/14/1999
• Est. Priority Date: 02/24/1998
• Status: Expired due to Term

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Dvir, Ran
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/028,740
• Time in Patent Office: 658 Days
• Field of Search: 365/103, 365/104, 365/168, 365/94, 365/63, 365/185.03
• US Class Current: 365/103
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 2211/5617 Multilevel ROM cell programmed by source, drain or gate contacting
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A column of read-only-memory (ROM) cells is programmed to store two or more bits of information in each cell by forming a plurality of coding (bit) lines adjacent to the column of cells, and selectively connecting the cells to the plurality of coding lines so that the different logic conditions defined by the two or more bits are represented by the coding lines that are connected to a memory cell.

Claims

1. A read-only-memory (ROM) comprising:

a column of memory cells having a plurality of rows, each memory cell storing one of a plurality of logic states, the plurality of logic states including a plurality of connected-defined logic states;

a plurality of word lines corresponding to the plurality of rows, each word line being connected to a corresponding memory cell in the column of memory cells;

a plurality of coding lines formed adjacent to the column of cells, each cell in the column of cells that stores a connection-defined logic state being connected to a coding line of the plurality of coding lines so that memory cells that store different connection-defined logic states are connected to different coding lines; and

a sense amp/converter connected to receive the plurality of coding lines, the sense amp/converter sensing a voltage on each coding line, and outputting a x-bit word that represents the logic state stored by a cell in the column of cells.

2. The ROM of claim 1 wherein a logic state is defined by a memory cell being unconnected to the coding lines.

3. The ROM of claim 2 wherein the memory cell includes a transistor having a gate.

4. The ROM of claim 3 wherein when a memory cell is to be unconnected to the coding lines, the gate of the transistor is unconnected to a word line.

5. The ROM of claim 2 wherein when a memory cell in the column of memory cells is to be unconnected to the coding lines, the memory cell includes no transistors.

6. The ROM of claim 1 wherein the sense amp/converter includes a plurality of AND gates connected to receive the logic state for each coding line.

7. The ROM of claim 1 wherein x is one less than the plurality of coding lines.

8. A read-only-memory (ROM) comprising:

a column of memory cells having a plurality of rows, each memory cell having a plurality of transistors, and storing one of a Plurality of logic states;

a plurality of word lines corresponding to the plurality of rows, each word line being connected to a corresponding memory cell in the column of memory cells; and

a plurality of coding lines formed adjacent to the column of cells, the coding lines being selectively connected to the plurality of transistors in each memory cell to define one of the plurality of logic states.

9. The ROM of claim 8 wherein a logic state is defined by the transistors in a memory cell being unconnected to the coding lines.

10. The ROM of claim 8 wherein a logic state is defined by a memory cell being unconnected to the coding lines.

11. The ROM of claim 10 wherein when a memory cell is to be unconnected to the coding lines, the memory cell includes no transistors.

12. The ROM of claim 10 wherein when a memory cell is to be unconnected to the coding lines, the memory cell is unconnected to a corresponding word line.

13. The ROM of claim 8 and further comprising a sense amp/converter connected to receive information from the plurality of coding lines, the sense amp/converter sensing a voltage on each coding line, and outputting a word that represents the logic state stored by a cell in the column of cells, a number of coding lines being greater than a number of bits in the word.

14. A read-only-memory (ROM) comprising:

a plurality of memory cells formed in a plurality of rows and a plurality of columns, each memory cell storing one of a plurality of logic states, the plurality of logic states including a plurality of connected-defined logic states;

a plurality of word lines corresponding to the plurality of rows of memory cells, each word line being connected to a corresponding row of memory cells;

a plurality of coding lines formed adjacent to each column of cells, each cell that stores a connection-defined logic state being connected to a coding line of the plurality of coding lines formed adjacent to a column of cells so that memory cells that store different connection-defined logic states are connected to different coding lines; and

a plurality of sense amp/converters corresponding to a plurality of columns of memory cells, each sense amp/converter receiving a corresponding plurality of coding lines, sensing a voltage on each of the coding lines of the corresponding plurality of coding lines, and outputting an x-bit word that represents the logic state stored in each cell.

15. The ROM of claim 14 wherein x is one less than the plurality of coding lines.

16. A read-only-memory (ROM) comprising:

a plurality of memory cells formed in a plurality of rows and a plurality of columns, each memory cell having a plurality of transistors, and storing one of a plurality of values;

a plurality of word lines corresponding to the plurality of rows of memory cells, each word line being connected to a corresponding row of memory cells; and

a plurality of coding lines formed adjacent to each column of cells, the coding lines adjacent to a column of cells being selectively connected to the plurality of transistors in each memory cell in the column to define one of the plurality of logic states.

17. The ROM of claim 16 wherein a logic state is defined by a memory cell being unconnected to the coding lines.

18. The ROM of claim 16 wherein a logic state is defined by the transistors in a memory cell being unconnected to the coding lines.

19. The ROM of claim 16 wherein a logic state is defined by a memory cell being unconnected to the coding lines.

20. The ROM of claim 19 wherein when a memory cell is to be unconnected to the coding lines, the memory cell includes no transistors.

21. The ROM of claim 19 wherein when a memory cell is to be unconnected to the coding lines, the memory cell is unconnected to a corresponding word line.

22. The ROM of claim 16 and further comprising a plurality of a sense amp/converters, each sense amp/converter being connected to receive information from the plurality of coding lines associated with a column of cells, the sense amp/converter sensing a voltage on each coding line, and outputting a word that represents the logic state stored by a cell in the column of cells, a number of coding lines being greater than a number of bits in the word.

23. A method for forming a read-only-memory (ROM), the method comprising the steps of:

forming a column of memory cells having a plurality of rows, each memory cell storing one of a plurality of values, the plurality of values including a plurality of connected values;

forming a plurality of word lines corresponding to the plurality of rows, each word line being connected to a corresponding memory cell in the column of memory cells;

forming a plurality of coding lines adjacent to the column of cells, each cell in the column of cells that stores a connected value being connected to a coding line of the plurality of coding lines, memory cells that store different connected values being connected to different coding lines;

forming a sense amp connected to receive the plurality of coding lines, the sense amp sensing a voltage on each coding line, and outputting a logic state for each coding line that represents the voltage sensed on each coding line; and

forming a converter connected to receive the logic state of each coding line output by the sense amp, the converter outputting an n-bit word that represents the logic state of each coding line output by the sense amp.

24. The method of claim 23 wherein a logic state is defined by a memory cell being unconnected to the coding lines.

25. The method of claim 24 wherein when a memory cell in the column of memory cells is to be unconnected to the coding lines, the memory cell includes no transistors.

26. The method of claim 24 wherein when a memory cell is to be unconnected to the coding lines, the memory cell is unconnected to a word line.