Verification of PN synchronization in a direct-sequence spread-spectrum digital communications system

• US 6,002,709 A
• Filed: 09/04/1998
• Issued: 12/14/1999
• Est. Priority Date: 11/21/1996
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: DSP Group Incorporated (Synaptics Incorporated)
• Inventors: Hendrickson, Alan F.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Maddox, Michael W.
• Application Number:
  US09/148,263
• Time in Patent Office: 466 Days
• Field of Search: 375/367, 375/208, 375/206, 375/358, 375/359, 375/362, 375/365, 375/368, 375/371, 375/373, 370/516, 370/510, 370/507, 370/509, 370/512, 370/513, 370/514, 370/515, 370/350, 370/503, 370/511, 370/345
• US Class Current: 375/150
• CPC Class Codes: H04L 1/24 Testing correct operation
• CPC Class Codes: H04L 7/0054 Detection of the synchronisation error by features other than the received signal transition by means of signal transition H04L7/033
• CPC Class Codes: H04L 7/0334 Processing of samples having at least three levels, e.g. soft decisions

Abstract

In a direct sequence spread spectrum digital communication receiver, a system and method for recovering and verifying the timing or phase of a pseudo-random noise (PN) sequence used for despreading received signals. In one embodiment, the method includes steps of: (a) determining an initial value of a received PN phase, (b) setting the receiver'"'"'s PN phase equal to the initial value of the received PN phase, (c) a first testing to verify that the receiver identifies a SYNC field within a testing time of predetermined duration, (d) a second testing, to verify that temporarily shifting the receiver'"'"'s PN phase results in a degraded correlation between the receiver'"'"'s PN sequence and the received signal, and (e) repeating steps (a)-(d) if either of the testings indicate that the receiver'"'"'s PN sequence is not correct. One embodiment of a system for recovering and verfying the PN timing includes an input for receiving a received spread-spectrum data stream, a maximal likelihood detection logic, a receiver PN clock, a despreading mixer that generates a narrowband signal from the spread-spectrum data stream, a first testing logic that generates a PASS output if it identifies a SYNC field in the narrowband signal during a testing period, and a second testing logic that temporarily shifts the receiver PN clock and generates a PASS output if the temporary shifting degrades the correlation between the receiver'"'"'s PN sequence and the received signal.

Claims

1. A method for matching a receiver PN (pseudo noise) sequence of a direct sequence spread spectrum communication receiver with a received PN sequence in a received data stream, wherein the received PN sequence has a received PN phase, wherein the receiver PN sequence has a receiver PN phase, wherein the data stream comprises a series of data frames, wherein the frames comprise a plurality of symbols, wherein the frames are received at substantially regular intervals, and wherein each frame in the series of frames includes a SYNC field at a predetermined location in the frame, the method comprising:

(a) determining an initial value of the received PN phase, wherein said determining an initial value uses a maximal likelihood detection to measure the received PN phase;

(b) setting the receiver PN phase equal to the initial value of the received PN phase after said determining an initial value,

(c) a first testing of the receiver PN phase to ensure that the receiver PN phase produces a receiver PN sequence that substantially matches the received PN sequence, wherein said first testing is performed after said setting the receiver PN phase equal to the initial value of the received PN phase, wherein said first testing comprises;

the receiver scanning the data stream for the SYNC field for a testing period of a predetermined duration, wherein said first testing indicates that the receiver PN sequence substantially matches the received PN sequence if the receiver identifies the SYNC field in the data stream during the testing period, and wherein said first testing indicates that the receiver PN sequence does not substantially match the received PN sequence if the receiver does not identify the SYNC field in the data stream during the testing period,

(d) a second testing of the receiver PN phase to ensure that the receiver PN phase produces a receiver PN sequence that substantially matches the received PN sequence, wherein said second testing is performed after said first testing, wherein said second testing is only performed if said first testing indicates that the receiver PN sequence substantially matches the received PN sequence, and wherein said second testing comprises;

making a first measurement of a correlation between the received PN sequence and the receiver PN sequence,

shifting the receiver PN phase after said making the first measurement,

making a second measurement of a correlation between the received PN sequence and the receiver PN sequence, wherein said making the second measurement occurs after said shifting the receiver PN phase, and

comparing the first measurement and the second measurement, wherein said second testing indicates that the receiver PN sequence substantially matches the received PN sequence if said first measurement is substantially greater than said second measurement, and wherein said second testing indicates that the receiver PN sequence does not match the received PN sequence if said first measurement is not substantially greater than said second measurement, and

(e) repeating said steps (a)-(d) if said first testing or said second testing indicates that the receiver PN sequence does not substantially match the received PN sequence.

2. The method of claim 1, wherein the predetermined duration for the testing period is greater than a time required to receive N number of frames, wherein N is greater than one, thereby providing a tolerance for bit errors in the SYNC field.

3. The method of claim 1, wherein the predetermined duration for the testing period is a time required to receive four frames.

4. The method of claim 3, wherein the predetermined duration for the testing period is a time required to receive two frames.

5. The method of claim 1, further comprising:

performing a fast tracking of the receiver PN phase if said first and second testing indicate that the receiver PN sequence substantially matches the received PN sequence, wherein said performing a fast tracking refines a synchronization of the receiver PN sequence with the received PN sequence; and

performing a slow tracking of the receiver PN phase after said performing a fast tracking, wherein said performing a slow tracking maintains a synchronization of the receiver PN sequence with the received PN sequence.

6. The method of claim 1, wherein said repeating said steps (a)-(d) is performed by hardware if said first testing indicates that the receiver PN sequence does not substantially match the received PN sequence.

7. The method of claim 1, wherein said repeating said steps (a)-(d) is performed by software if said second testing indicates that the receiver PN sequence does not substantially match the received PN sequence.

8. In a direct sequence spread spectrum communication receiver, a PN (pseudo noise) timing recovery system for synchronizing a receiver PN sequence with a received PN sequence in a received data stream, wherein the received PN sequence has a received PN phase, wherein the receiver PN sequence has a receiver PN phase, wherein the data stream comprises a series of data frames, wherein the frames comprise a plurality of symbols, wherein the frames are received at substantially regular intervals, and wherein each frame in the series of frames includes a SYNC field at a predetermined location in the frame, the system comprising:

an input for receiving the received data stream;

a maximum-likelihood (ML) detection logic coupled to said input and configured to measure an initial value of the received PN phase of the received PN sequence in the received data stream;

a receiver PN clock that controls the receiver PN phase of the receiver PN sequence, wherein said receiver PN clock is coupled to said ML detection logic, and wherein said receiver PN clock is operable to set the receiver PN phase substantially equal to the initial value of the received PN phase;

a despreading mixer coupled to said input and to said receiver PN clock, wherein said despreading mixer despreads the received data stream with the receiver PN sequence to generate a narrowband signal;

a first testing logic coupled to said despreading mixer and to said ML detection logic, wherein said first testing logic is operable to monitor the narrowband signal for the SYNC field during a predetermined testing period after the PN clock setting the receiver PN phase substantially equal to the initial value of the received PN phase, and wherein said first testing logic generates a first PASS output if said first testing logic identifies the SYNC field in the data stream during the testing period;

second testing logic coupled to said despreading mixer, to said receiver PN clock, and to said ML detection logic, wherein said second testing logic is operable to adjust the receiver PN clock to temporarily shift the receiver PN sequence, wherein said second testing logic includes;

a correlator operable to measure a correlation between the received PN sequence and the receiver PN sequence,

a memory coupled to said correlator and operable to store (1) a first measurement of a correlation between the received PN sequence and the receiver PN sequence and (2) a second measurement of a correlation between the received PN sequence and a temporarily shifted receiver PN sequence, and

a comparator coupled to said memory, wherein said comparator generates a second PASS output if said first measurement is substantially greater than said second measurement;

wherein said ML detection logic is operable to measure a new initial value of the received PN phase if said first testing logic does not generate the first PASS output or if said second testing logic does not generate the second PASS output.

9. The system of claim 8, wherein one or more of said ML detection logic, said first testing logic, and said second testing logic comprise digital logic hardware.

10. The system of claim 8, wherein one or more of said ML detection logic, said first testing logic, and said second testing logic are implemented in software on a digital signal processor, a microprocessor, a microcontroller, or an embedded processor.