Programmable digital circuits

• US 6,003,054 A
• Filed: 02/18/1998
• Issued: 12/14/1999
• Est. Priority Date: 07/28/1987
• Status: Expired due to Fees

• Current Assignee: Kanazawa Institute Of Technology
• Original Assignee: Kanazawa Institute Of Technology
• Inventors: Murakoshi, Hodaka, Nishi, Shuji, Oshima, Hiroyasu
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US09/025,258
• Time in Patent Office: 664 Days
• Field of Search: 708/1, 708/100, 708/200, 708/230-236, 708/306-307, 708/490, 708/446, 708/443, 708/444, 708/800-804
• US Class Current: 708/230
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 7/48 using non-contact-making devices, e.g. tube, solid state device; using unspecified devices

Abstract

A composite digital network including an integrating circuit, a summing circuit and a coefficient circuit is formed as an integrated circuit that provides a selected one of digital arithmetic circuits that perform different arithmetic operations depending upon coefficients of the coefficient circuits. A plurality of units of such composite digital networks may be connected in rows, columns or layers to provide an expanded network. In a method of producing such a composite digital network, basic digital arithmetic circuits that respectively correspond to various types of basic analog arithmetic circuits are defined based on Kirchhoff'"'"'s rules, for example, and these basic digital arithmetic circuits are coupled to each other via a coefficient circuit to thus provide a generic digital arithmetic integrated circuit.

Claims

1. A generic digital arithmetic integrated circuit comprising a composite digital network that includes at least one integrating circuit, at least one summing circuit and at least one coefficient circuit, said composite digital network being formed as a fixed integrated circuit, wherein at least one coefficient of said at least one coefficient circuit is changed so that the composite digital network provides a selected one of digital arithmetic circuits having different computing functions.

2. A generic digital arithmetic integrated circuit as defined in claim 1, wherein said composite digital network selectively constitutes a (said) basic digital arithmetic first-lag integration circuit in which a coefficient circuit (K₁), a summing circuit (M₁) and an integrating circuit (S₁) are connected in series, and a coefficient circuit (K₂) is connected between the other input terminal of said summing circuit (M₁) and an output terminal of said integrating circuit (S₁).

3. A generic digital arithmetic integrated circuit as defined in claim 1, wherein said composite digital network selectively constitutes a (said) basic digital arithmetic proportional integration circuit in which an integrating circuit (S₂), a coefficient circuit (K₃) and a summing circuit (M₂) are connected in series, and a coefficient circuit (K₄) is connected between an input terminal of said integrating circuit (S₂) and the other input terminal of said summing circuit (M₂).

4. A generic digital arithmetic integrated circuit as defined in claim 1, wherein said composite digital network selectively constitutes a (said) basic digital arithmetic approximate differentiation circuit in which a coefficient circuit (K₅) and a summing circuit (M₃) are connected in series, and an integrating circuit (S₃) and a coefficient circuit (K₆) are connected in series between an output terminal and the other input terminal of said summing circuit (M₃).

5. A generic digital arithmetic integrated circuit as defined in claim 1, wherein said composite digital network selectively constitutes a (said) basic digital arithmetic proportional differentiation circuit in which a coefficient circuit (K₇), a summing circuit (M₄), a coefficient circuit (K₈) and a summing circuit (M₅) are connected in series, and an integrating circuit (S₄) and a coefficient circuit (K₉) are connected in series between an output terminal and the other input terminal of said summing circuit (M₄), while a coefficient circuit (K₁₀) is connected between an input terminal of said coefficient circuit (K₇) and the other input terminal of said summing circuit (M₅).

6. A generic digital arithmetic integrated circuit as defined in claim 1, wherein said composite digital network selectively constitutes a (said) basic digital arithmetic phase compensation circuit in which a coefficient circuit (K₁₁), a summing circuit (M₆) and a summing circuit (M₇) are connected in series, and an integrating circuit (S₅) and a coefficient circuit (K₁₂) are connected between an output terminal and the other input terminal of said summing circuit (M₆), while said integrating circuit (S₅) and a coefficient circuit (K₁₃) are connected in series between the output terminal of said summing circuit (M₆) and the other input terminal of said summing circuit (M₇).

7. A generic digital arithmetic integrated circuit as defined in claim 1, wherein said composite digital network selectively constitutes a (said) first basic digital arithmetic non-oscillation circuit in which a coefficient circuit (K₁₄), a summing circuit (M₈) and an integrating circuit (S₆) are connected in series, and an integrating circuit (S₇), a coefficient circuit (K₁₅) and a summing circuit (M₉) are connected in series between an output terminal of said integrating circuit (S₆) and the other input terminal of said summing circuit (M₈), while a coefficient circuit (K₁₆) is connected between the output terminal of the integrating circuit (S₆) and the other input terminal of the summing circuit (M₉).

8. A generic digital arithmetic integrated circuit as defined in claim 1, wherein said composite digital network selectively constitutes a (said) second basic digital arithmetic non-oscillation circuit in which a coefficient circuit (K₁₇), a coefficient circuit (K₁₈), a summing circuit (M₁₀) and a summing circuit (M₁₁) are connected in series, and an integrating circuit (S₈) is connected between an input terminal of said coefficient circuit (K₁₈) and the other input terminal of said summing circuit (M₁₀), while a coefficient circuit (K₁₉), a summing circuit (M₁₂) and a coefficient circuit (K₂₀) are connected in series between the input terminal of the coefficient circuit (K₁₈) and the other input terminal of said summing circuit (M₁₁), and an integrating circuit (S₉) and a coefficient circuit (K₂₁) are connected in series between an output terminal and the other input terminal of said summing circuit (M₁₂).

9. A generic digital arithmetic integrated circuit as defined in claim 1, wherein each of at least one of said coefficient circuits used for providing a selected one of the digital arithmetic circuits or basic digital arithmetic circuits comprises a logic switch capable of switching a coefficient k of said each coefficient circuit between 1 and 0.

10. A generic digital arithmetic integrated circuit as defined in claim 1, wherein said composite digital network is provided with a summing circuit for circuit expansion and connection, which is connected to at least one of input and output terminals of the composite digital network.

11. A generic digital arithmetic integrated circuit comprising a plurality of circuit units each comprising a composite digital network that includes at least one integrating circuit, at least one summing circuit and at least one coefficient circuit, wherein at least one coefficient of said at least one coefficient circuit is changed so that the composite digital network provides a selected one of digital arithmetic circuits having different computing functions, and wherein said plurality of circuit units are arranged and connected to each other in at least one direction of rows, columns and layers, to provide an expanded network, so that said circuit units are formed as a fixed integrated circuit.

12. A generic digital arithmetic integrated circuit comprising a composite digital network that includes at least one integrating circuit, at least one summing circuit and at least one coefficient circuit, said composite digital network being formed as a fixed integrated circuit, wherein at least one coefficient of said at least one coefficient circuit is changed so that said composite digital network selectively provides at least one of two or more basic digital arithmetic circuits, out of a plurality of types of basic digital arithmetic circuits having different computing functions.

13. A generic digital arithmetic integrated circuit as defined in claim 12, wherein said plurality of types of basic digital arithmetic circuits comprise a basic digital arithmetic first-order lag integration circuit, a basic digital arithmetic proportional integration circuit, a basic digital arithmetic approximate differentiation circuit, a basic digital arithmetic proportional differentiation circuit, a basic digital arithmetic phase compensation circuit, a first basic digital arithmetic non-oscillation circuit and a second basic digital arithmetic non-oscillation circuit, each of which includes at least one integrating circuit, at least one summing circuit and at least one coefficient circuit.

14. A generic digital arithmetic integrated circuit comprising a plurality of circuit units each comprising a composite digital network that includes at least one integrating circuit, at least one summing circuit and at least one coefficient circuit, wherein at least one coefficient of said at least one coefficient circuit being changed so that said composite digital network selectively provides at least one of two or more basic digital arithmetic circuits, out of a plurality of types of basic digital arithmetic circuits having different computing functions, and wherein said plurality of circuit units are arranged and connected to each other in at least one direction of rows, columns and layers, to provide an expanded network, so that said circuit units are formed as a fixed integrated circuit.

15. A generic digital arithmetic integrated circuit comprising a composite digital network that is formed as a fixed integrated circuit wherein a coefficient circuit (K₂₂), a summing circuit (M₁₃), a coefficient circuit (K₂₃), a summing circuit (M₁₄) and a summing circuit (M₁₅) are connected in series, and an integrating circuit (S₁₀), a coefficient circuit (K₂₄) and a summing circuit (M₁₆) are connected in series between an output terminal and the other input terminal of said summing circuit (M₁₃), wherein an integrating circuit (S₁₀) and a coefficient circuit (K₂₅) are connected in series between the output terminal of said summing circuit (M₁₃) and the other input terminal of said summing circuit (M₁₄), and an integrating circuit (S₁₁) and a coefficient circuit (K₂₆) are connected in series between an output terminal of said coefficient circuit (K₂₅) and the other input terminal of said summing circuit (M₁₆), and wherein a coefficient circuit (K₂₇), a summing circuit (M₁₇) and a coefficient circuit (K₂₈) are connected in series between the output terminal of the summing circuit (M₁₃) and the other input terminal of the summing circuit (M₁₅), and an integrating circuit (S₁₂) and a coefficient circuit (K₂₉) are connected in series between an output terminal and the other input terminal of said summing circuit (M₁₇), at least one coefficient of the coefficient circuits being changed so that said composite digital network provides a selected one of a basic digital arithmetic first-order lag integration circuit, a basic digital arithmetic proportional integration circuit, a basic digital arithmetic approximate integration circuit, a basic digital arithmetic proportional differentiation circuit, a basic digital arithmetic phase compensation circuit, a first basic digital arithmetic non-oscillation circuit, and a second basic digital arithmetic non-oscillation circuit.

16. A generic digital arithmetic integrated circuit comprising a plurality of circuit units each of which comprises a composite digital network wherein a coefficient circuit (K₂₂), a summing circuit (M₁₃), a coefficient circuit (K₂₃), a summing circuit (M₁₄) and a summing circuit (M₁₅) are connected in series, and an integrating circuit (S₁₀), a coefficient circuit (K₂₄) and a summing circuit (M₁₆) are connected in series between the output terminal and the other input terminal of said summing circuit (M₁₃), wherein an integrating circuit (S₁₀) and a coefficient circuit (K₂₅) are connected in series between an output terminal of said summing circuit (M₁₃) and the other input terminal of said summing circuit (M₁₄), and an integrating circuit (S₁₁) and a coefficient circuit (K₂₆) are connected in series between an output terminal of said coefficient circuit (K₂₅) and the other input terminal of said summing circuit (M₁₆), and wherein a coefficient circuit (K₂₇), a summing circuit (M₁₇) and a coefficient circuit (K₂₈) are connected in series between the output terminal of said summing circuit (M₁₃) and the other input terminal of said summing circuit (M₁₅), and an integrating circuit (S₁₂) and a coefficient circuit (K₂₉) are connected in series between an output terminal and the other input terminal of said summing circuit (M₁₇), at least one coefficient of said coefficient circuits being changed so that said composite digital network provides a selected one of a basic digital arithmetic first-order lag integration circuit, a basic digital arithmetic proportional integration circuit, a basic digital arithmetic approximate integration circuit, a basic digital arithmetic proportional differentiation circuit, a basic digital arithmetic phase compensation circuit, a first basic digital arithmetic non-oscillation circuit, and a second basic digital arithmetic non-oscillation circuit, said plurality of circuit units being arranged and connected to each other in at least one direction of rows, columns and layers, to provide an expanded network, so that said circuit units are formed as a fixed integrated circuit.

17. A generic digital arithmetic integrated circuit comprising a composite digital network that is formed as a fixed integrated circuit wherein a coefficient circuit (K₃₀), a summing circuit (M₁₈), a coefficient circuit (K₃₁), a summing circuit (M₁₉) and a summing circuit (M₂₀) are connected in series, and an integrating circuit (S₁₃) and a coefficient circuit (K₃₂) are connected in series between an output terminal and the other input terminal of said summing circuit (M₁₈), and wherein said integrating circuit (S₁₃) and a coefficient circuit (K₃₃) are connected in series between the output terminal of the summing circuit (M₁₈) and the other input terminal of the summing circuit (M₁₉), and a coefficient circuit (K₃₄) is connected between an input terminal of said coefficient circuit (K₃₀) and the other input terminal of said summing circuit (M₂₀), at least one coefficient of said coefficient circuits being changed so that said composite digital network provides a selected one of a basic digital arithmetic first-order lag integration circuit, a basic digital arithmetic proportional integration circuit, a basic digital arithmetic approximate integration circuit, a basic digital arithmetic proportional differentiation circuit, and a basic digital arithmetic phase compensation circuit.

18. A generic digital arithmetic integrated circuit comprising a composite digital network that is formed as a fixed integrated circuit wherein a coefficient circuit (K₃₀), a summing circuit (M₁₈), a coefficient circuit (K₃₁), a summing circuit (M₁₉) and a summing circuit (M₂₀) are connected in series, and an integrating circuit (S₁₃) and a coefficient circuit (K₃₂) are connected in series between an output terminal and the other input terminal of said summing circuit (M₁₈), wherein said integrating circuit (S₁₃) and a coefficient circuit (K₃₃) are connected in series between the output terminal of the summing circuit (M₁₈) and the other input terminal of the summing circuit (M₁₉), and a coefficient circuit (K₃₄) is connected between an input terminal of said coefficient circuit (K₃₀) and the other input terminal of said summing circuit (M₂₀), and wherein a first lead (X) and a second lead (Y) are connected to the other input terminal of said summing circuit (M₁₈) and the other input terminal of said summing circuit (M₂₀), respectively, at least one coefficient of said coefficient circuits being changed so that said composite digital network provides a selected one of a basic digital arithmetic first-order lag integration circuit, a basic digital arithmetic proportional integration circuit, a basic digital arithmetic approximate integration circuit, a basic digital arithmetic proportional differentiation circuit, and a basic digital arithmetic phase compensation circuit.

19. A generic digital arithmetic integrated circuit comprising a plurality of circuit units each of which comprises a composite digital network wherein a coefficient circuit (K₃₀), a summing circuit (M₁₈), a coefficient circuit (K₃₁), a summing circuit (M₁₉) and a summing circuit (M₂₀) are connected in series, and an integrating circuit (S₁₃) and a coefficient circuit (K₃₂) are connected in series between an output terminal and the other input terminal of said summing circuit (M₁₈), and wherein said integrating circuit (S₁₃) and a coefficient circuit (K₃₃) are connected in series between the output terminal of the summing circuit (M₁₈) and the other input terminal of the summing circuit (M₁₉), and a coefficient circuit (K₃₄) is connected between an input terminal of said coefficient circuit (K₃₀) and the other input terminal of said summing circuit (M₂₀), at least one coefficient of said coefficient circuits being changed so that said composite digital network provides a selected one of a basic digital arithmetic first-order lag integration circuit, a basic digital arithmetic proportional integration circuit, a basic digital arithmetic approximate integration circuit, a basic digital arithmetic proportional differentiation circuit, and a basic digital arithmetic phase compensation circuit, said plurality of circuit units being arranged and connected to each other in at least one direction of rows, columns and layers, to provide an expanded network, so that said circuit units are formed as a fixed integrated circuit.

20. A generic digital arithmetic integrated circuit comprising first and second composite digital networks (Ws1) (Ws2) having the same circuit pattern wherein a coefficient circuit (K₃₀), a summing circuit (M₁₈), a coefficient circuit (K₃₁), a summing circuit (M₁₉) and a summing circuit (M₂₀) are connected in series, and an integrating circuit (S₁₃) and a coefficient circuit (K₃₂) are connected in series between an output terminal and the other input terminal of said summing circuit (M₁₈), and wherein said integrating circuit (S₁₃) and a coefficient circuit (K₃₃) are connected in series between the output terminal of the summing circuit (M₁₈) and the other input terminal of the summing circuit (M₁₉), and a coefficient circuit (K₃₄) is connected between an input terminal of said coefficient circuit (K₃₀) and the other input terminal of said summing circuit (M₂₀), an output terminal of said summing circuit (M₂₀) of said first composite digital network (Ws1) being connected to the input terminal of said coefficient circuit (K₃₀) of said second composite digital network (Ws2), an output terminal of said summing circuit (M₂₀) of said second composite digital network (Ws2) being connected to the other input terminal of said summing circuit (M₁₈) of said first composite digital network (Ws1), said first and second composite digital networks (Ws1) (Ws2) being formed as a fixed integral circuit that provides a first basic digital arithmetic non-oscillation circuit by setting a coefficient of each of the coefficient circuits in the first and second composite digital networks (Ws1) (Ws2).

21. A generic digital arithmetic integrated circuit comprising first and second composite digital networks (Ws1) (Ws2) having the same circuit pattern wherein a coefficient circuit (K₃₀), a summing circuit (M₁₈), a coefficient circuit (K₃₁), a summing circuit (M₁₉) and a summing circuit (M₂₀) are connected in series, and an integrating circuit (S₁₃) and a coefficient circuit (K₃₂) are connected in series between an output terminal and the other input terminal of said summing circuit (M₁₈), and wherein said integrating circuit (S₁₃) and a coefficient circuit (K₃₃) are connected in series between the output terminal of the summing circuit (M₁₈) and the other input terminal of the summing circuit (M₁₉), and a coefficient circuit (K₃₄) is connected between an input terminal of said coefficient circuit (K₃₀) and the other input terminal of said summing circuit (M₂₀), an output terminal of said summing circuit (M₂₀) of said first composite digital network (Ws1) being connected to the other input terminal of said summing circuit (M₂₀) of said second composite digital network (Ws2), the input terminal of said coefficient circuit (K₃₀) of said first composite digital network being connected to the input terminal of said coefficient circuit (K₃₀) of said second composite digital network (Ws2), said first and second composite digital networks (Ws1) (Ws2) being formed as a fixed integrated circuit that provides a second basic digital arithmetic non-oscillation circuit by setting a coefficient of each of the coefficient circuits in the first and second composite digital networks (Ws1) (Ws2).

22. A generic digital arithmetic integrated circuit comprising first and second composite digital networks (Ws1) (Ws2) having the same circuit pattern wherein a coefficient circuit (K₃₀), a summing circuit (M₁₈), a coefficient circuit (K₃₁), a summing circuit (M₁₉) and a summing circuit (M₂₀) are connected in series, and an integrating circuit (S₁₃) and a coefficient circuit (K₃₂) are connected in series between an output terminal and the other input terminal of said summing circuit (M₁₈), and wherein said integrating circuit (S₁₃) and a coefficient circuit (K₃₃) are connected in series between the output terminal of the summing circuit (M₁₈) and the other input terminal of the summing circuit (M₁₉), and a coefficient circuit (K₃₄) is connected between an input terminal of said coefficient circuit (K₃₀) and the other input terminal of said summing circuit (M₂₀), an output terminal of said summing circuit (M₂₀) of said first composite digital network (Ws1) being connected to the other input terminal of said summing circuit (M₂₀) of said second composite digital network (Ws2), an output terminal of said coefficient circuit (K₃₀) of said first composite digital network (Ws1) being connected to an input terminal of said summing circuit (M₃₀) of said second composite digital network (Ws2), said first and second composite digital networks (Ws1) (Ws2) being formed as a fixed integrated circuit that provides a second basic digital arithmetic non-oscillation circuit by setting a coefficient of each of the coefficient circuits in the first and second composite digital networks (Ws1) (Ws2).

23. A generic digital arithmetic integrated circuit comprising first, second and third composite digital networks (Ws1) (Ws2) (Ws3) having the same circuit pattern wherein a coefficient circuit (K₃₀), a summing circuit (M₁₈), a coefficient circuit (K₃₁), a summing circuit (M₁₉) and a summing circuit (M₂₀) are connected in series, and an integrating circuit (S₁₃) and a coefficient circuit (K₃₂) are connected in series between an output terminal and the other input terminal of said summing circuit (M₁₈), and wherein said integrating circuit (S₁₃) and a coefficient circuit (K₃₃) are connected in series between the output terminal of the summing circuit (M₁₈) and the other input terminal of the summing circuit (M₁₉), and a coefficient circuit (K₃₄) is connected between an input terminal of said coefficient circuit (K₃₀) and the other input terminal of said summing circuit (M₂₀), an output terminal of said summing circuit (M₂₀) of said first composite digital network (Ws1) being connected to the input terminal of said coefficient circuit (K₃₀) of each of said second composite digital network (Ws2) and said third composite digital network (Ws3), an output terminal of said summing circuit (M₂₀) of said second composite digital network (Ws2) being connected to the other input terminal of said summing circuit (M₂₀) of said third composite digital network (Ws3), said first, second and third composite digital networks (Ws1) (Ws2) (Ws3) being formed as a fixed integrated circuit that provides a second basic digital arithmetic non-oscillation circuit by setting a coefficient of each of the coefficient circuits in the first, second and third composite digital networks (Ws1) (Ws2) (Ws3).

24. A method for producing a generic digital arithmetic integrated circuit, comprising the steps of:

converting a plurality of types of basic analog arithmetic circuits having different computing functions into respective equivalent analog circuits;

obtaining expressions representing current-voltage relationships on input and output sides of each of said equivalent analog circuits;

defining a plurality of basic digital arithmetic circuits that respectively correspond to said basic analog arithmetic circuits, each of said basic digital arithmetic circuits being designed by locating digital arithmetic elements according to the expressions of the current-voltage relationships; and

connecting said plurality of basic digital arithmetic circuits via at least one coefficient circuit each having an ON/OFF switching function.