Method for attachment or integration of a bios device into a computer system using a local bus

• US 6,003,103 A
• Filed: 09/30/1997
• Issued: 12/14/1999
• Est. Priority Date: 09/30/1997
• Status: Expired due to Term

• Current Assignee: Mei California, Inc. (Micron Technology, Inc.)
• Original Assignee: Micro Electronics Incorporated
• Inventors: Klein, Dean A.
• Primary Examiner(s): Auve, Glenn A.
• Assistant Examiner(s): Vo, Tim T.
• Application Number:
  US08/940,215
• Time in Patent Office: 805 Days
• Field of Search: 395/750.01, 395/728, 395/821, 395/306, 395/733, 395/288, 395/651, 395/652, 395/653, 395/303, 395/301, 395/302
• US Class Current: 710/306
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

Chipset or a device for attachment of the ROM BIOS within the system architecture. Although normally attached to the ISA bus, the ROM BIOS may be attached to an alternate bus (typically a higher-performance bus) located within the system, thereby potentially eliminating the ISA bus from the computer system.

Claims

1. A method of accessing a BIOS device in a computer system having a central processing unit, core logic for controlling operations on a mezzanine bus, wherein the mezzanine bus normally operates in a first mode, and a BIOS device on the mezzanine bus, the method comprising the acts of:

bypassing logic that initiates mezzanine bus cycles in the first operating mode;

then presenting an address to the BIOS device by placing the address on the mezzanine bus;

receiving data stored in the BIOS device by sampling a portion of the mezzanine bus;

transferring the data to the central processing unit; and

then returning the mezzanine bus to the first operating mode.

2. The method of claim 1, further comprising the act of:

ensuring that no other device is the master of the mezzanine bus before the act of presenting an address to the BIOS device.

3. The method of claim 2, further comprising the act of sequencing a plurality of low-order bits of the address presented to the BIOS device so that data from more than one addressable location is read from the BIOS device before the data is transferred to the central processing unit.

4. The method of claim 3, further comprising the act of transferring at least some of the contents of the BIOS device to faster memory at system start-up.

5. A method of executing BIOS instructions in a computer system having a PCI bus with AD lines, a BIOS device that is on the PCI bus and that has BIOS instructions stored therein, core logic having a PCI state machine that initiates normal PCI bus cycles, and a central processing unit, the method comprising the acts of:

bypassing the PCI state machine such that a normal PCI bus cycle is not initiated;

placing an address on the PCI bus, wherein the address occupies some of the AD lines on the PCI bus so that the address is presented to the BIOS device;

waiting for the BIOS device to place the addressed data on the PCI bus;

reading the addressed data from the BIOS device by sampling a different set of AD lines on the PCI bus; and

transferring the data from the BIOS device to the central processing unit.

6. The method of claim 5, further comprising the act of:

transferring at least some of the contents of the BIOS device to faster memory at system start-up.

7. The method of claim 6, wherein the act of reading the addressed data from the BIOS device includes the act of:

reading the addressed data from a BIOS device having eight-bit data units stored in an eighteen-bit address space.

8. In a logic device for controlling BIOS operations in a computer system having a central processing unit, a mezzanine bus, and a BIOS device on the mezzanine bus, and a state machine for initiating mezzanine bus cycles, the method comprising the acts of:

bypassing the state machine such that a mezzanine bus cycle is not initiated;

ensuring that no other device is the master of the mezzanine bus before the act of presenting an address to the BIOS device;

presenting an address to the BIOS device by placing the address on the mezzanine bus;

receiving data stored in the BIOS device by sampling a portion of the mezzanine bus;

transferring the data to the central processing unit and

then allowing the state machine to initiate a mezzanine bus cycle.

9. The method of claim 8, further comprising the act of:

sequencing a plurality of low-order bits on the address so that data from more than one addressable location is read from the BIOS device before the data is transferred to the central processing unit.

10. The method of claim 9, further comprising the act of:

transferring at least some of the contents of the BIOS device to faster memory at system start-up.