Circuitry for providing external access to signals that are internal to an integrated circuit chip package

• US 6,003,107 A
• Filed: 09/10/1996
• Issued: 12/14/1999
• Est. Priority Date: 09/10/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Lesartre, Gregg B., Knebel, Patrick, Bockhaus, John W., Perez, Paul L., Ranson, Gregory L.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): Vo, Tim T.
• Application Number:
  US08/707,936
• Time in Patent Office: 1,190 Days
• Field of Search: 395/800.38, 395/800.39, 395/800.4, 395/311, 395/250, 395/325, 395/800, 395/288, 395/800.22, 395/800.02, 395/588, 364/231.9, 364/489, 364/232.21, 364/237.2, 364/238, 364/230, 364/200, 326/41, 326/93, 326/39, 326/101
• US Class Current: 710/316
• CPC Class Codes: G06F 7/02 Comparing digital values G06F7/06, G06F7/22, G06F7/38 take precedence

Abstract

Circuitry for providing external access to signals that are internal to an integrated circuit chip package. A plurality of N:1 multiplexers are physically distributed throughout the integrated circuit die. Each of the multiplexers has its N inputs coupled to a nearby set of N nodes within the integrated circuit, and each of the multiplexers is coupled to a source of select information operable to select one node from the set of N nodes for external access. Each of the multiplexers has its output coupled to an externally-accessible chip pad. The integrated circuit is a microprocessor, and the source of select information may include a storage element. If so, additional circuitry is provided for writing data from a register of the microprocessor to the storage element using one or more microprocessor instructions. Each multiplexer may be coupled to a different source of select information, or all multiplexers may be coupled to the same select information. Moreover, a fixed set of interconnect traces may be provided to couple a fixed set of nodes to an additional set of externally-accessible chip pads. One or more M:1 multiplexers may also be provided, having their M inputs coupled to M different outputs of the N:1 multiplexers. Each of the M:1 multiplexers may be coupled to a second source of select information. Preferably, the outputs of the M:1 multiplexers will be coupled to a circuitry for facilitating debug and performance monitoring of the integrated circuit.

Claims

1. Circuitry for providing external access to signals that are internal to an integrated circuit chip package, said circuitry comprising;

a plurality of N;

1 multiplexers physically distributed throughout the integrated circuit die, each of said plural multiplexers having all of its N inputs coupled to a nearby set of N nodes within the integrated circuit, each of said plural multiplexers coupled to a source of select information operable to select one node from said set of N nodes for external access, and each of said plural multiplexers having its output coupled directly to an externally-accessible chip pad; and

at least one M;

1 multiplexer having its M inputs coupled directly to M different outputs of said N;

1 multiplexers, each of said M;

1 multiplexers coupled to a second source of select information and having its output coupled to a circuitry for facilitating debug of the integrated circuit.

2. The circuitry of claim 1, wherein said integrated circuit is a microprocessor, wherein said source of select information comprises a storage element, and wherein said circuitry further comprises:

circuitry for writing data from a register of said microprocessor to said storage element using at least one microprocessor instruction.

3. The circuitry of claim 1, wherein each of said plural multiplexers is coupled to a different source of select information.

4. The circuitry of claim 1, wherein each of said M:

1 multiplexers is coupled to a different second source of select information.

5. The circuitry of claim 1, wherein said source of select information comprises a storage element, and further comprising circuitry for facilitating debug of the integrated circuit, said circuitry for facilitating debug of the integrated circuit operable to change the contents of said storage element responsive to the occurrence of an event.

6. The circuitry of claim 1, wherein said second source of select information comprises a second storage element, and wherein said circuitry for facilitating debug of the integrated circuit is operable to change the contents of said second storage element responsive to the occurrence of an event.

7. The circuitry of claim 1, wherein said source of select information comprises a storage element, and said second source of select information comprises a second storage element, and wherein said circuitry for facilitating debug of the integrated circuit is operable to change the contents of said storage element and said second storage element responsive to the occurrence of an event.

8. The circuitry of claim 2, wherein each of said plural multiplexers is coupled to a different source of select information, and wherein said circuitry for writing data is operable to write data to each of said different sources of select information independently.

9. The circuitry of claim 2, further comprising a fixed set of interconnect traces coupling a fixed set of nodes of said integrated circuit to an additional set of externally-accessible chip pads.

10. The circuitry of claim 2,

wherein said second source of select information comprises a second storage element;

and

wherein said circuitry for writing data is also operable to write data to said second storage element using at least one microprocessor instruction.

11. The circuitry of claim 8, further comprising a fixed set of interconnect traces coupling a fixed set of nodes of said integrated circuit to an additional set of externally-accessible chip pads.

12. The circuitry of claim 10, wherein each of said M:

1 multiplexers is coupled to a different second source of select information;

wherein each of said different second sources of select information comprises a second storage element; and

wherein said circuitry for writing data is also operable to write data to each of said second sources of select information independently using at least one microprocessor instruction.

13. The circuitry of claim 12, further comprising a fixed set of interconnect traces coupling a fixed set of nodes of said integrated circuit to an additional set of externally-accessible chip pads.

14. An integrated circuit, comprising;

a first plurality of M multiplexers physically distributed throughout the integrated circuit, each of said M multiplexers having N inputs directly coupled to N nodes within the integrated circuit, and each of said M multiplexers having an output coupled directly to a unique externally accessible chip pad;

a second plurality of O multiplexers, each of said O multiplexers having P inputs directly coupled to P outputs of said M multiplexers;

wherein each of said O multiplexers is operable to select one of P outputs of a subset of said M multiplexers for feedback to said integrated circuit.

15. An integrated circuit, comprising;

a first multiplexer subsystem comprising a plurality of first multiplexers physically distributed throughout the integrated circuit, said first multiplexer subsystem having N inputs each coupled to one of N nodes within the integrated circuit and having M outputs coupled directly to externally-accessible chip pads;

a first source of select information operably associated with said first multiplexer subsystem to select a subset of said N inputs for connection to said M outputs;

a second multiplexer subsystem having M inputs directly coupled to said M outputs of said first multiplexer subsystem and having O outputs coupled to input nodes of said integrated circuit, said second multiplexer subsystem having at least one multiplexer having a plurality of inputs, at least two of said plurality of inputs being directly coupled to at least two of said M outputs; and

a second source of select information operably associated with said second multiplexer subsystem to select a subset of said M inputs for connection to said O outputs.

16. Circuitry for providing external access to signals that are internal to an integrated circuit chip package, comprising;

a plurality of N nodes;

a plurality of first multiplexers physically distributed throughout the integrated circuit chip package, each of said first multiplexers having a plurality of inputs and an output;

a first set of leads, each of said first leads directly interconnecting one of said plurality of N nodes with one of said inputs of one of said first multiplexers;

a plurality of chip pads;

a second set of leads, each of said second leads directly interconnecting an output of one of said first multiplexers with one of said plurality of chip pads;

a second set of multiplexers, each of said second multiplexers having a plurality of inputs and an output;

a third set of leads, each of said third leads directly interconnecting one of said second leads with an input of one of said second multiplexers, wherein more than one of said second leads is connected to each of said second multiplexers;

a second set of nodes; and

a fourth set of leads, each of said fourth leads directly interconnecting an output of one of said second multiplexers with one of said second set of nodes.

17. Circuitry for providing external access to signals that are internal to an integrated circuit chip package, said circuitry comprising;

a plurality of N;

1 multiplexers, each of said plural multiplexers having its N inputs coupled to a set of N nodes within the integrated circuit, and each of said plural multiplexers coupled to a source of select information operable to select one node from said set of N nodes for external access, and each of said plural multiplexers having its output coupled dirty to an extemally-accessible chip pad; and

at least one M;

1 multiplexer having its M inputs coupled directly to M different outputs of said N;

1 mutiplexers, each of said M;

1 multiplexes coupled to a second source of select information and having its output coupled to a circuitry for facilitating debug of the integrated circuit.

18. The circuitry of claim 17, wherein the plurality of N:

1 multiplexers are physically distributed throughout the integrated circuit die, and each of said plural multiplexers having its N inputs coupled to a nearby set of N nodes within the integrated circuit.

19. The circuitry of claim 18, wherein each of said plural multiplexers has all of its N inputs coupled to a nearby set of N nodes within the integrated circuit.