Memory controller and method for clearing or copying memory utilizing register files to store address information

• US 6,003,112 A
• Filed: 06/30/1997
• Issued: 12/14/1999
• Est. Priority Date: 06/30/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Tetrick, Raymond S.
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US08/886,079
• Time in Patent Office: 897 Days
• Field of Search: 711/165, 711/166, 711/135, 711/5, 711/100, 711/154, 365/230.03
• US Class Current: 711/100
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 9/5016 the resource being the memory

Abstract

A memory controller and method for clearing and copying memory in a computer system. The memory controller includes a register file having fields that store information that defines a first block of memory and indicates whether the first block of memory is to be cleared or copied to a first destination, and a first resource unit that clears or copies the first block of memory to the first destination as indicated by the first register file. The register file may store the starting address and length or size of the first block of memory, or a starting and ending address of the first block of memory. The name of the operation to be performed by the first resource unit may also be stored in the register file. A clearing operation may be performed by invalidating cache data that corresponds to the block of memory and writing zeros into the block of memory. A second register file and resource unit may also be provided and a second block of memory cleared or copied simultaneously with the first block of memory.

Claims

1. A memory controller comprising:

a resource allocating unit coupled to a plurality of resource units, the resource allocating unit to indicate which of the plurality of resource units are available at a particular instant in time;

a first register file comprising fields to store information that defines a first block of memory locations in a memory; and

a first resource unit of the plurality of resource units, coupled to the first register file, to clear the first block of memory locations as defined in the first register file by writing predetermined data to the first block of memory locations.

2. The memory controller of claim 1, wherein the resource allocating unit comprises an index register to store an indicator that indicates which of the plurality of resource units are available.

3. The memory controller of claim 1, wherein the first register file comprises:

an address field to store a starting address of the first block of memory locations; and

a length field to store a size of the first block of memory locations.

4. The memory controller of claim 1, wherein the first register file comprises an address field to store a starting address and an ending address of the first block of memory locations.

5. The memory controller of claim 1, further comprising:

a second register file comprising fields to store information that defines a second block of memory locations in the memory; and

a second resource unit of the plurality of resource units, coupled to the second register file, to clear the second block of memory locations as defined by the second register file simultaneously as the first resource unit clears the first block of memory locations.

6. A memory controller comprising:

a resource allocating unit coupled to a plurality of resource units the resource allocating unit to indicate which of the plurality of resource units are available at a particular instant in time;

a first register file comprising fields to store information that defines a first block of memory locations in a memory and a first destination of where to copy contents of the first block of memory locations; and

a first resource unit of the plurality of resource units, coupled to the first register file, to copy the contents of the first block of memory locations to the first destination as defined in the first register file.

7. The memory controller of claim 6, wherein the memory controller comprises an index register to store an indicator that indicates which of the plurality of resource units are available.

8. The memory controller of claim 6, wherein the first register file comprises:

an address field to store a starting address of the first block of memory locations and a destination address of where to copy the contents of the first block of memory locations; and

a length field to store a size of the first block of memory locations.

9. The memory controller of claim 6, wherein the first register file comprises an address field to store a starting address and an ending address of the first block of memory locations and a destination address of where to copy the contents of the first block of memory locations.

10. The memory controller of claim 6, further comprising:

a second register file comprising fields to store information that defines a second block of memory locations in the memory and a second destination of where to copy contents of the second block of memory locations; and

a second resource unit of the plurality of resource units, coupled to the second register file, to copy the contents of the second block of memory locations as defined by the second register file to the second destination simultaneously as the first resource unit copies the contents of the first block of memory locations.

11. A memory controller comprising:

a first register file comprising fields to store information that defines a first block of memory locations in a memory and indicates whether the first block of memory locations is to be cleared or whether contents of the first block of memory locations are to be copied to a first destination; and

a first resource unit, coupled to the first register file, to clear the first block of memory locations or copy the contents of the first block of memory locations to the first destination as indicated by the first register file.

12. The memory controller of claim 11, further comprising an index register coupled to the first resource unit, the index register to store an indicator that indicates whether the first resource unit is available.

13. The memory controller of claim 11, wherein the first register file comprises:

an operation field to store a name of an operation to be performed by the first resource unit;

an address field to store a starting address of the first block of memory locations and a destination address of where to copy the contents of the first block of memory locations if the name of the operation is a copy operation; and

a length field to store a size of the first block of memory locations.

14. The memory controller of claim 11, wherein the first register file comprises:

an operation field to store a name of an operation to be performed by the first resource unit; and

an address field to store a starting address and an ending address of the first block of memory locations and a destination address of where to copy the contents of the first block of memory locations if the name of the operation is a copy operation.

15. The memory controller of claim 11, further comprising:

a second register file comprising fields to store information that defines a second block of memory locations in the memory and indicates whether the second block of memory locations is to be cleared or whether contents of the second block of memory locations are to be copied to a second destination; and

a second resource unit, coupled to the second register file and the first resource unit, to clear the second block of memory locations or to copy the contents of the second block of memory locations to the second destination as indicated by the second register file simultaneously as the first resource unit clears the first block of memory locations or copies the contents of the first block of memory locations.

16. A computer system, comprising:

a first bus;

a processor coupled to the first bus;

a memory;

a second bus; and

a bridge memory controller, coupled to the first bus, the memory, and the second bus, comprising;

a first register file comprising fields to store information that defines a first block of memory locations in the memory and indicates whether the first block of memory locations is to be cleared or whether contents of the first block of memory locations are to be copied to a first destination, and

a first resource unit to clear the first block of memory locations or copy the contents of the first block of memory locations to the first destination as indicated by the first register file.

17. The computer system of claim 16, wherein the bridge memory controller further comprises an index register to store an indicator that indicates whether the first resource unit is available.

18. The computer system of claim 16, wherein the first register file comprises:

an operation field to store a name of an operation to be performed by the first resource unit;

an address field to store a starting address of the first block of memory locations and a destination address of where to copy the contents of the first block of memory locations if the name of the operation is a copy operation; and

a length field to store a size of the first block of memory locations.

19. The computer system of claim 16, wherein the first register file comprises:

an operation field to store a name of an operation to be performed by the first resource unit; and

an address field to store a starting address and an ending address of the first block of memory locations and a destination address of where to copy the contents of the first block of memory locations if the name of the operation is a copy operation.

20. The computer system of claim 16, wherein the bridge memory controller further comprises:

a second register file comprising fields to store information that defines a second block of memory locations in the memory and indicates whether the second block of memory locations is to be cleared or whether contents of the second block of memory locations are to be copied to a second destination; and

a second resource unit that clears the second block of memory locations or copies the contents of the second block of memory locations to the second destination as indicated by the second register file simultaneously as the first resource unit clears the first block of memory locations or copies the contents of the first block of memory locations.

21. A method for clearing and copying a block of memory locations in a memory, comprising:

storing, in an operation field in a register file of a bridge memory controller, a name of an operation to be performed on the block of memory locations in the memory;

storing, in a starting address field in the register file of the bridge memory controller, a starting address of the block of memory locations;

storing, in a destination address field in the register file of the bridge memory controller, a destination address of where the block of memory locations is to be copied if the name of the operation to be performed is a copy operation;

reading data from the block of memory locations and copying the data to the destination address if the name of the operation to be performed is the copy operation; and

invalidating cache data in a processor, the cache data corresponding to the block of memory locations, and writing zeros into the block of memory locations if the name of the operation to be performed is a clear operation.

22. The method of claim 21, wherein a resource unit of the bridge memory controller performs at least one of reading of and copying of the data, and invalidating of the cache data and writing of the zeros, the method further comprising storing an indicator in an index register of the bridge memory controller that indicates whether the resource unit is available.

23. The method of claim 21, wherein reading of the data from the block of memory is achieved by a resource unit of the bridge memory controller by issuing a Read For Ownership command.

24. The method of claim 21, wherein invalidating of the cache data in the processor is achieved by a resource unit of the bridge memory controller by issuing a Memory Invalidate command.