Memory system with global address translation

• US 6,003,123 A
• Filed: 02/10/1998
• Issued: 12/14/1999
• Est. Priority Date: 09/28/1994
• Status: Expired due to Fees

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Dally, William J., Keckler, Stephen W., Carter, Nicholas P.
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): Verbrugge, Kevin
• Application Number:
  US09/021,658
• Time in Patent Office: 672 Days
• Field of Search: 711/147, 711/202, 711/203, 711/206, 711/207, 711/209
• US Class Current: 711/207
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 12/1045 associated with a data cache
• CPC Class Codes: G06F 12/1072 Decentralised address translation, e.g. in distributed shared memory systems
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism

Abstract

A multiprocessor system having shared memory uses guarded pointers to identify protected segments of memory and permitted access to a location specified by the guarded pointer. Modification of pointers is restricted by the hardware system to limit access to memory segments and to limit operations which can be performed within the memory segments. Global address translation is based on grouping of pages which may be stored across multiple nodes. The page groups are identified in the global translation of each node and, with the virtual address, identify a node in which data is stored. Pages are subdivided into blocks and block status flags are stored for each page. The block status flags indicate whether a memory location may be read or written into at a particular node and indicate to a home node whether a remote node has written new data into a location.

Claims

1. In a parallel processing system, a method of addressing data across plural processor nodes comprising:

applying a virtual address to a global translation buffer to identify a mapping of a page group of plural pages across a set of plural but less than all processor nodes in the system, the page group containing the physical page to which the virtual address corresponds; and

from the virtual address and mapping, determining a destination node as a node within the set of processor nodes which contains the physical page to which the virtual address corresponds.

2. A method as claimed in claim 1 further comprising forwarding a message to the destination node.

3. A method as claimed in claim 2 further comprising, at the destination node, translating the virtual address to a physical address.

4. A method as claimed in claim 1 wherein each page group is specified by a group size.

5. A method as claimed in claim 4 wherein the group size is logarithmically encoded.

6. A method as claimed in claim 1 wherein the translation buffer specifies a start node and the range of the set of nodes.

7. A method as claimed in claim 6 wherein the range is specified in plural dimensions.

8. A method as claimed in claim 7 wherein the range is logarithmically encoded in each of the plural dimensions.

9. A method as claimed in claim 8 wherein the translation buffer specifies the number of pages of the page group per node of the set of nodes.

10. A method as claimed in claim 6 wherein the translation buffer specifies the number of pages of the page group per node of the set of nodes.

11. A method as claimed in claim 1 wherein the translation buffer specifies the number of pages of the page group per node of the set of nodes.

12. A data processing system comprising a plurality of processor nodes, each processor node comprising:

a global translation buffer for identifying relative to a virtual address a mapping of a page group of plural pages to a set of plural processor node s in the system, the page group containing the physical page to which the virtual address corresponds;

electronics which determines, from the virtual address and the identified mapping, a destination node as a node within the set of processor nodes having the physical address corresponding to the virtual address.