System and method for handling interrupt and exception events in an asymmetric multiprocessor architecture

• US 6,003,129 A
• Filed: 08/19/1996
• Issued: 12/14/1999
• Est. Priority Date: 08/19/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Nguyen, Le, Mohamed, Moataz A., Park, Heon-Chul, Song, Seungyeon Peter
• Primary Examiner(s): Ramirez, Ellis B.
• Application Number:
  US08/699,294
• Time in Patent Office: 1,212 Days
• Field of Search: 395/591, 395/738, 395/739, 395/740, 395/800.3, 395/800.28
• US Class Current: 712/244
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00

Abstract

A multiprocessor computer system includes a plurality of processors, called asymmetric processors, having mutually dissimilar control and data-handling characteristics. The asymmetric processors are controlled by a single operating system although the individual processors have instruction sets that are mutually independent of the other processors. The multiprocessor computer system uses a multiprocessor architectural definition of interrupt and exception handling in which a processor, called a data or vector processor, having a large machine state and a large data width detects exceptions but defers interrupt and exception handling operations to another processor, called a control processor, having a small machine state and data width. The small machine state and small data width of the control processor are well suited for executing operating system programs such as interrupt and exception handling since control programs typically involve monitoring and control of individual flags and pointers. The data processor enters an idle state upon reset and when an exception is detected to facilitate system design and programming, and to simplify synchronization of the processors at system reset. A multiprocessor computer system includes a control processor which reads and writes control and status registers within a data processor. The control processor thus controls the operation of the data processor during execution of an operating system or application programs. The control processor has access to the control and status registers of the data processor independent of the data processor execution so that the same control and status registers may be accessed by the control processor and the data processor in parallel.

Claims

1. A computer system comprising:

a plurality of mutually-coupled processors including processors having mutually dissimilar control and data-handling characteristics;

a common operating system for controlling the plurality of processors;

an interruption and exception handler for operating in conjunction with the operating system including;

an interrupt and exception detector operating on a first processor of the plurality of processors for detecting interrupt and exception conditions of the first processor; and

an interrupt and exception subhandler operating on a second processor of the plurality of processors for detecting interrupt and exception conditions of the first processor and for handling the interrupt and exception conditions of the first processor and the second processor in combination.

2. A computer system according to claim 1 wherein:

the second processor is a control processor having a defined data path width; and

the first processor is a vector processor having a wide data path width that is substantially larger than the data path width of the second processor.

3. A computer system according to claim 1 wherein:

the interrupt and exception detector operating on the first processor of the plurality of processors deactivates the first processor to an idle state in response to a detected exception.

4. A computer system according to claim 1 wherein:

the second processor has read and write access to control and status registers of the first processor.

5. A computer system according to claim 4 wherein:

the interrupt and exception detector operating on the first processor of the plurality of processors deactivates the first processor to an idle state in response to a detected exception; and

the second processor is constrained to have read and write access to control and status registers of the first processor when the first processor is in the idle state.

6. A computer system comprising:

a plurality of mutually-coupled processors including processors having mutually dissimilar control and data-handling characteristics;

a common operating system for controlling the plurality of processors;

an interruption and exception handler for operating in conjunction with the operating system including;

an interrupt and exception detector operating on a first processor of the plurality of processors for detecting interrupt and exception conditions of the first processor, the interrupt and exception detector disabling the first processor into an idle state in response to detection of an exception, the first processor being activated from the idle state by signals from another processor of the plurality of processors.

7. A computer system according to claim 6 wherein the interrupt and exception handler further comprises:

an interrupt and exception subhandler operating on a second processor of the plurality of processors and controlling an interrupt and exception response of the first processor.

8. A computer system according to claim 7 wherein:

the second processor is a control processor having a defined data path width; and

the first processor is a vector processor having a wide data path width that is substantially larger than the data path width of the second processor.

9. A computer system comprising:

a plurality of mutually-coupled processors including processors having mutually dissimilar control and data-handling characteristics;

a common operating system for controlling the plurality of processors;

an interruption and exception handler for operating in conjunction with the operating system on a first processor and a second processor of the plurality of processors, the second processor having read and write access to control and status registers of the first processor.

10. A computer system according to claim 9 wherein the interruption and exception handler further comprises:

an interrupt and exception detector operating on the first for detecting interrupt and exception conditions of the first processor.

11. A computer system according to claim 9 wherein the interruption and exception handler further comprises:

an interrupt and exception subhandler operating on the second processor for detecting interrupt and exception conditions of the first processor and for handling the interrupt and exception conditions of the first processor and the second processor in combination.

12. A computer system according to claim 9 wherein:

the second processor is a control processor having a defined data path width; and

the first processor is a vector processor having a wide data path width that is substantially larger than the data path width of the second processor.

13. A computer system according to claim 9 wherein:

the interrupt and exception detector operating on the first processor of the plurality of processors deactivates the first processor to an idle state in response to a detected exception; and

the second processor is constrained to have read and write access to control and status registers of the first processor when the first processor is in the idle state.

14. A method of handling interrupts and exceptions in a computer system including asymmetric processors comprising:

operating a first processor of the asymmetric processors as a controlled processor;

operating a second processor of the asymmetric processors as a controlling processor;

detecting an exception condition in the controlled processor;

sending an interrupt request signal from the controlled processor to the controlling processor indicating the exception condition of the controlled processor;

invoking an idle state in the controlled processor in response to the exception condition; and

operating the controlling processor to handle the exception condition of the controlled processor.

15. A method according to claim 14 further comprising:

detecting a reset of the computer system; and

invoking an idle state of the controlled processor in response to the computer system reset.

16. A method according to claim 15 wherein the step of operating the controlling processor to handle the exception condition of the controlled processor further comprises:

operating the controlling processor to initialize registers of the controlled processor when the controlled processor is in the idle state in response to the interrupt request signal from the controlled processor; and

operating the controlling processor to execute an instruction for activating the controlled processor into a run state when the registers of the controlled processor are initialized.

17. A method according to claim 16 wherein the step of operating the controlling processor to handle the exception condition of the controlled processor further comprises:

operating the controlling processor to read register information from the controlled processor;

determining a type of exception based on the register information; and

operating the controlling processor to handle the exception based on the exception type.

18. A method according to claim 14 further comprising:

operating the controlling processor to read and write registers of the controlled processor when the controlled processor is in the idle state.

19. A method according to claim 14 further comprising:

operating the controlling processor and the controlled processor using a single operating system; and

executing mutually independent instruction sets in the controlling processor and the controlled processor.

20. A method according to claim 14 wherein:

the controlled processor is a vector processor or data processor having a large machine state and a large data width; and

the controlling processor is a control processor having a machine state and data width that are substantially smaller than the machine state and data width of the controlled processor.

21. A multimedia computer system comprising:

a control processor;

a vector or data processor coupled to the control processor, the vector or data processor having a large machine state and a large data width in comparison to the control processor;

a coprocessor interface coupled between the control processor and the vector or data processor;

an exception detector coupled to the vector or data processor for detecting an exception condition and, in response to the exception condition detection, sending an interrupt request to the control processor and disabling the vector or data processor to an idle state; and

an exception handler coupled to the control processor for receiving the interrupt request and, in response to the interrupt request, handling the exception condition of the vector or data processor.

22. A multimedia computer system according to claim 21 wherein the coprocessor interface comprises:

a plurality of registers that are readable and writeable by the control processor and the vector or data processor;

a decoder for decoding instructions of the control processor instruction set and detecting extension instructions that are executable on the coprocessor interface; and

a state machine for executing the extension instructions.

23. A multimedia computer system according to claim 21 wherein:

the control processor and the vector or data processor have mutually dissimilar control and data-handling characteristics.

24. A multimedia computer system according to claim 23 wherein:

the control processor has a defined data path width; and

the vector or data processor has a wide data path width that is substantially larger than the data path width of the control processor.

25. A multimedia computer system according to claim 21 further comprising:

a host processor coupled to the control processor, the host processor including program codes for controlling operations of the control processor.