System and method for handling interrupt and exception events in an asymmetric multiprocessor architecture
First Claim
1. A computer system comprising:
- a plurality of mutually-coupled processors including processors having mutually dissimilar control and data-handling characteristics;
a common operating system for controlling the plurality of processors;
an interruption and exception handler for operating in conjunction with the operating system including;
an interrupt and exception detector operating on a first processor of the plurality of processors for detecting interrupt and exception conditions of the first processor; and
an interrupt and exception subhandler operating on a second processor of the plurality of processors for detecting interrupt and exception conditions of the first processor and for handling the interrupt and exception conditions of the first processor and the second processor in combination.
4 Assignments
0 Petitions
Accused Products
Abstract
A multiprocessor computer system includes a plurality of processors, called asymmetric processors, having mutually dissimilar control and data-handling characteristics. The asymmetric processors are controlled by a single operating system although the individual processors have instruction sets that are mutually independent of the other processors. The multiprocessor computer system uses a multiprocessor architectural definition of interrupt and exception handling in which a processor, called a data or vector processor, having a large machine state and a large data width detects exceptions but defers interrupt and exception handling operations to another processor, called a control processor, having a small machine state and data width. The small machine state and small data width of the control processor are well suited for executing operating system programs such as interrupt and exception handling since control programs typically involve monitoring and control of individual flags and pointers. The data processor enters an idle state upon reset and when an exception is detected to facilitate system design and programming, and to simplify synchronization of the processors at system reset. A multiprocessor computer system includes a control processor which reads and writes control and status registers within a data processor. The control processor thus controls the operation of the data processor during execution of an operating system or application programs. The control processor has access to the control and status registers of the data processor independent of the data processor execution so that the same control and status registers may be accessed by the control processor and the data processor in parallel.
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Citations
25 Claims
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1. A computer system comprising:
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a plurality of mutually-coupled processors including processors having mutually dissimilar control and data-handling characteristics; a common operating system for controlling the plurality of processors; an interruption and exception handler for operating in conjunction with the operating system including; an interrupt and exception detector operating on a first processor of the plurality of processors for detecting interrupt and exception conditions of the first processor; and an interrupt and exception subhandler operating on a second processor of the plurality of processors for detecting interrupt and exception conditions of the first processor and for handling the interrupt and exception conditions of the first processor and the second processor in combination. - View Dependent Claims (2, 3, 4, 5)
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6. A computer system comprising:
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a plurality of mutually-coupled processors including processors having mutually dissimilar control and data-handling characteristics; a common operating system for controlling the plurality of processors; an interruption and exception handler for operating in conjunction with the operating system including; an interrupt and exception detector operating on a first processor of the plurality of processors for detecting interrupt and exception conditions of the first processor, the interrupt and exception detector disabling the first processor into an idle state in response to detection of an exception, the first processor being activated from the idle state by signals from another processor of the plurality of processors. - View Dependent Claims (7, 8)
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9. A computer system comprising:
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a plurality of mutually-coupled processors including processors having mutually dissimilar control and data-handling characteristics; a common operating system for controlling the plurality of processors; an interruption and exception handler for operating in conjunction with the operating system on a first processor and a second processor of the plurality of processors, the second processor having read and write access to control and status registers of the first processor. - View Dependent Claims (10, 11, 12, 13)
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14. A method of handling interrupts and exceptions in a computer system including asymmetric processors comprising:
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operating a first processor of the asymmetric processors as a controlled processor; operating a second processor of the asymmetric processors as a controlling processor; detecting an exception condition in the controlled processor; sending an interrupt request signal from the controlled processor to the controlling processor indicating the exception condition of the controlled processor; invoking an idle state in the controlled processor in response to the exception condition; and operating the controlling processor to handle the exception condition of the controlled processor. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A multimedia computer system comprising:
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a control processor; a vector or data processor coupled to the control processor, the vector or data processor having a large machine state and a large data width in comparison to the control processor; a coprocessor interface coupled between the control processor and the vector or data processor; an exception detector coupled to the vector or data processor for detecting an exception condition and, in response to the exception condition detection, sending an interrupt request to the control processor and disabling the vector or data processor to an idle state; and an exception handler coupled to the control processor for receiving the interrupt request and, in response to the interrupt request, handling the exception condition of the vector or data processor. - View Dependent Claims (22, 23, 24, 25)
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Specification