Data processor with a privileged state firewall and method therefore

• US 6,003,133 A
• Filed: 11/17/1997
• Issued: 12/14/1999
• Est. Priority Date: 11/17/1997
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Moyer, William C., Moughanni, Claude, Aslam, Taimur
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): HAMDAN, WASSEEM H
• Application Number:
  US08/972,069
• Time in Patent Office: 757 Days
• Field of Search: 713/200, 713/201, 714/815, 365/185.04, 340/568.1
• US Class Current: 726/4
• CPC Class Codes: H04L 63/0245 Filtering by information in the payload
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A data processor (20) includes a firewall circuit (50) that monitors privilege level changes or transitions between privilege modes, such as from user mode and user space into supervisory or privileged mode and operating system space. The firewall circuit starts a timer (54) whenever a central processing unit (22) enters supervisor mode. If the timer (54) determines the passage of a predetermined time while the central processing unit remains continuously in supervisory mode without re-entering user mode, a predefined security policy is invoked. For example, the security policy may require at this point that the data processor (20) is to be reset. Different timer (54) time-out values and different security policies can be set for different types of privilege level changes. In one embodiment, a default time-out value provides protection for multiple types of privilege level changes.

Claims

1. A data processor with a privileged state firewall, comprising:

a central processing unit for executing a plurality of instructions and accessing memory in response to an execution of said plurality of instructions, said central processing unit characterized as operating in a first mode and a second mode which is at a lower privilege level than said first mode;

when in said first mode said central processing unit allows access to a protected system resource by one of said plurality of instructions;

when in said second mode said central processing unit inhibits access to said protected system resource by any of said plurality of instructions; and

a firewall circuit coupled to said central processing unit, for recognizing when said central processing unit changes from said second mode to said first mode, and for providing a firewall exception trigger signal if said central processing unit remains in said first mode continuously for a predetermined time.

2. The data processor of claim 1 wherein said central processing unit further provides a status signal which identifies a selected one of a plurality of privilege level chances, and said firewall circuit further activates one of a plurality of policy output signals in response to said status signal.

3. The data processor of claim 1 wherein said central processing unit further provides a status signal which identifies a selected one of a plurality of privilege level changes, and said firewall circuit further activates said firewall exception trigger signal if said central processing unit remains in said first mode continuously for one of a plurality of predetermined times selected in response to said status signal.

4. The data processor of claim 3 wherein said status signal further identifies a selected one of a plurality of privilege level changes, and said firewall circuit further activates one of a plurality of policy output signals in response to said status signal.

5. The data processor of claim 1 wherein said firewall circuit comprises:

a control logic circuit having an input terminal coupled to said central processing unit for receiving a status signal which identifies a selected one of a plurality of privilege level changes, and an output terminal for providing a selection signal in response to said status signal;

a table for storing a plurality of values corresponding to a plurality of privilege level changes, having an input terminal for receiving a selection signal, and an output terminal for providing a value selected by said selection signal at said predetermined time; and

timer means coupled to said table for providing said firewall exception trigger signal said predetermined time after said central processing unit changes from said second mode to said first mode and remains in said first mode continuously.

6. The data processor of claim 5 wherein said timer means includes reset means for resetting said timer means in response to said central processing unit returning to said second mode.

7. The data processor of claim 1 wherein said firewall circuit comprises:

a control logic circuit having an input terminal coupled to said central processing unit for receiving a status signal which identifies a selected one of a plurality of privilege level changes, and an output terminal for providing a selection signal in response to said status signal;

a table for storing a plurality of values corresponding to a plurality of privilege level changes, having an input terminal for receiving a selection signal, and an output terminal for providing a value selected by said selection signal;

timer means coupled to said table for providing said firewall exception trigger signal said predetermined time after said central processing unit changes from said second mode to said first mode; and

a security policy logic circuit coupled to said table for providing one of a plurality of policy output signals in response to said value selected by said selection signal after receiving said firewall exception trigger signal.

8. The data processor of claim 7 wherein said table comprises a plurality of entries corresponding to one of said plurality of privilege level changes, wherein each entry defines a predetermined time associated with a corresponding privilege level change.

9. The data processor of claim 7 wherein said table comprises an entry corresponding to at least two of said plurality of privilege level changes, wherein said entry defines a predetermined time associated with said at least two of said plurality of privilege level changes.

10. The data processor of claim 1 further comprising:

a memory for storing said plurality of instructions, wherein said memory stores a first portion of said plurality of instructions which are executed in said first mode, and a second portion of said plurality of instructions which are executed in said second mode.

11. The data processor of claim 10 wherein said memory further stores a first plurality of data values associated with said first portion of said plurality of instructions, and a second plurality of data values associated with said second portion of said plurality of instructions.

12. A method for providing a privileged state firewall in a data processor, comprising the steps of:

recognizing when a central processing unit enters a first mode which is at a higher privilege level than a second mode, said central processing unit allowing access to a protected system resource by one of a plurality of instructions in said first mode and inhibiting access to said protected system resource by any of said plurality of instructions when in said second mode;

measuring a passage of time while said central processing unit is continuously in said first mode;

determining when said passage of time exceeds a predetermined time; and

activating a firewall exception trigger signal in response to said step of determining.

13. The method of claim 12 further comprising the steps of:

identifying one of a plurality of privilege level changes which caused said central processing unit to enter said first mode; and

using a value corresponding to said one of said plurality of privilege level changes as said predetermined time.

14. The method of claim 12 further comprising the steps of:

identifying one of a plurality of privilege level changes which caused said central processing unit to enter said first mode; and

using a value corresponding to said one of said plurality of privilege level changes to activate one of a plurality of policy output signals.

15. The method of claim 14 further comprising the step of resetting said central processing unit in response to a selected one of said plurality of policy output signals.

16. The method of claim 14 further comprising the step of destroying an integrated circuit having said central processing unit integrated thereon in response to a selected one of said plurality of policy output signals.

17. The method of claim 14 further comprising the step of disabling a peripheral circuit which is integrated with said central processing unit on a single integrated circuit in response to a selected one of said plurality of policy output signals.

18. In a data processor comprising a central processing unit for executing a plurality of instructions and accessing memory in response to an execution of said plurality of instructions, said central processing unit characterized as operating in a first mode and a second mode which is at a lower privilege level than said first mode, and a timer for counting a predetermined number of periods of a clock signal and providing an output signal in response thereto, the improvement wherein:

the timer is part of a firewall circuit and the firewall circuit enables a counting of clock signals by said timer when said central processing unit changes from said second mode to said first mode, and resets said timer when said central processing unit changes from said first mode to said second mode.

19. The data processor of claim 18 wherein said central processing unit further provides a status signal which identifies a selected one of a plurality of privilege level changes, and said firewall circuit further activates one of a plurality of policy output signals in response to said status signal.

20. The data processor of claim 18 wherein said central processing unit further provides a status signal which identifies a selected one of a plurality of privilege level changes, and said firewall circuit further activates a firewall exception trigger signal if said central processing unit remains in said first mode continuously for one of a plurality of predetermined times selected in response to said status signal.

21. The data processor of claim 20 wherein said status signal further identifies a selected one of a plurality of privilege level changes, and said firewall circuit further activates one of a plurality of policy output signals in response to said status signal.