Semiconductor memory device allowing repair of a defective memory cell with a redundant circuit in a multibit test mode

• US 6,003,148 A
• Filed: 01/13/1997
• Issued: 12/14/1999
• Est. Priority Date: 05/30/1996
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ito, Takashi, Yamauchi, Tadaaki, Asakura, Mikio
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Iqbal, Nadeem
• Application Number:
  US08/781,387
• Time in Patent Office: 1,065 Days
• Field of Search: 371/10.3, 371/10.2, 371/21.2, 371/21.1, 371/20.4, 371/22.5, 371/27.5, 371/40.2, 395/183.01, 395/183.06, 395/182.04, 395/182.05, 395/183.18, 395/185.01, 395/185.07, 365/201, 365/200, 365/189.01, 365/189.07, 324/73.1
• US Class Current: 714/711
• CPC Class Codes: G11C 29/34 Accessing multiple bits simultaneously

Abstract

In a predetermined multibit test mode, a multibit test circuit 114 issues determination result data pairs RDM0 and /RDM0 to RDM3 and /RDM3, each of which corresponds to match/mismatch of logics of data read from memory cells selected by one column select line in corresponding one of memory cell plane blocks. In each memory cell plane block, memory cell columns selected by one single column select line can be replaced as a unit. The unit of memory cell columns containing a defective memory cell is replaced in accordance with determination result data RDM0 and /RDM0 to RDM3 and /RDM3.

Claims

1. A semiconductor memory device comprising:

control means for controlling a normal mode operation and a test mode operation of said semiconductor memory device in accordance with an externally applied control signal;

a first number of memory cell blocks,

each of said memory cell blocks including;

a plurality of memory cells arranged in a matrix form,

row select means for selecting a memory cell row in accordance with an externally applied address signal,

column select means for simultaneously selecting a second number of memory cell columns in accordance with said externally applied address signal, and

read means for reading said second number of storage data from said memory cells belonging to said selected memory cell row and said selected memory cell columns in both said normal and said test mode operation;

a plurality of data input/output terminals including said first number of terminal groups each provided for a corresponding one of said first number of memory cell blocks;

each terminal group having said second number of data input/output terminals each outputting a corresponding one of said second number of storage data in said normal mode; and

test means for receiving said second number of storage data from each of said memory cell blocks, and being controlled by said control means to issue either one of a first determination signal corresponding to a result of comparison of said storage data sent from all the memory cell blocks and said first number of second determination signals each corresponding to a result of comparison performed on said second number of storage data in said test mode operation;

said test means issuing each of said first number of second determination signals to a predetermined data input/output terminal of a corresponding terminal group.

2. The semiconductor memory device according to claim 1, wherein

each of said memory cell blocks further includes:

a spare memory cell column unit including said second number of memory cell columns; and

spare column select means for storing an externally set address value and, when said externally applied address signal corresponds to said set address value, selecting the corresponding spare memory cell column unit.

3. The semiconductor memory device according to claim 2, wherein

said test means includes:

the first number of first logic circuits each receiving said second number of storage data and issuing said second determination signal having a logic level corresponding to the result of comparison; and

a second logic circuit receiving said first number of second determination signals and issuing said first determination signal having a logic level corresponding to the result of comparison.

7. The semiconductor memory device according to claim 1, wherein

said test means issues said first determination signal to a predetermined data input/output terminal belonging to one of said terminal groups.

4. A semiconductor memory device comprising:

control means for controlling a normal mode operation and a test mode operation of said semiconductor memory device in accordance with an externally applied control signal;

a first number of memory blocks;

each of said memory cell blocks including;

a plurality of memory cells arranged in a matrix form,

row select means for selecting a memory cell row in accordance with an externally applied address signal,

column select means responsive to said externally applied address signal for simultaneously selecting memory cell column units of m (m;

natural number) in number, each unit including memory cell columns of n (n;

natural number) in number,

read means for reading storage data of (n×

m) in number from said plurality of memory cells belonging to said selected memory cell row and said selected memory cell columns in both said normal and said test mode operation, and

data match detecting means of n in number for generating a match detection signal,

the ith (1≦

i≦

n) data match detecting means receiving said storage data of m in number from said ith memory cell column in each of said memory cell column units, and issuing a match detection signal depending on match/mismatch of said received storage data;

each of said data match detecting means including;

a signal interconnection for transmitting one of said storage data of m in number in said normal mode operation and transmitting said match detection signal in said test mode operation,

precharge means for setting a predetermined potential on said signal interconnection prior to reading of said storage data,

discharge means of m in number for discharging said signal interconnection in accordance with a corresponding one of said storage data of m in number in said normal mode operation and in accordance with corresponding storage data of m in number respectively in said test mode operation; and

test means for receiving said match detection signals of n in number from each of said memory cell blocks, and being controlled by said control means to issue either one of a first determination signal corresponding to a result of comparison of said match detection signals sent from all of said memory cell blocks and said first number of second determination signals each corresponding to a result of comparison performed on said match detection signals of n in number in said test mode operation.

5. The semiconductor memory device according to claim 4, wherein

each of said memory cell blocks further includes:

spare memory cell columns including a plurality of memory cell column groups each having said memory cell column units of m in number; and

spare column select means for storing an externally set address value and, when said externally applied address signal corresponds to said set address value, selecting the corresponding group of said spare memory cell columns.

6. The semiconductor memory device according to claim 4, wherein

said test means includes:

the first number of first logic circuits each receiving said match detection signals of n in number and issuing said second determination signal having a logic level corresponding to the result of comparison; and

a second logic circuit receiving said first number of second determination signals and issuing said first determination signal having a logic level corresponding to the result of comparison.

8. The semiconductor memory device according to claim 4, further comprising:

a plurality of data input/output terminals including said first number of terminal groups each provided for a corresponding one of said first number of memory cell blocks, and

each of said terminal groups having said second number of data input/output terminals each outputting a corresponding one of said second number of storage data in said normal mode;

said test means issuing each of said first number of second determination signals to a predetermined data input/output terminal of a corresponding terminal group.

9. The semiconductor memory device according to claim 8, wherein

said test means issues said first discrimination signal to a predetermined data input/output terminal belonging to one of said terminal groups.

10. A semiconductor memory device comprising;

(a) a plurality of memory cell groups;

(b) a plurality of data bus groups, each including a plurality of data buses,

each of the plurality of data buses receiving data from a corresponding one of the memory cell groups in both a normal mode and a test mode;

(c) a plurality of terminal groups provided corresponding to the plurality of data bus groups respectively,

each of the plurality of terminal groups including a plurality of terminals provided corresponding to the plurality of data buses included in a corresponding one of the plurality of data bus groups respectively,

each of the plurality of terminals outputting data transmitted by a corresponding one of the plurality of data buses in the normal mode; and

(d) a multibit test circuit producing a plurality of test results corresponding to the plurality of data bus groups respectively,

each of the plurality of test results indicating whether data transmitted by the data buses included in a corresponding one of the plurality of data bus groups are in agreement and being accessible through the terminal included in a corresponding one of the plurality of terminal groups in the test mode.

11. The semiconductor memory device according to claim 10, wherein

the multibit test circuit generated a determination result data for being applied to one of the plurality of terminals in the test mode, the determination result data indicating whether data transmitted by the data buses included in predetermined groups of the plurality of data bus groups are in agreement.

12. The semiconductor memory device according to claim 11, further comprising:

(e) a buffer circuit applying data transmitted by the plurality of data buses included in the plurality of data bus groups to the plurality of terminals included in the plurality of terminal groups respectively in the normal mode,

the buffer circuit applying each of test result data to the terminal included in the corresponding one of the plurality of terminal groups when a multibit test signal indicates a first multibit test mode in the test mode, and applying the determination result data to one of the plurality of terminals when the multibit test signal indicates a second multibit test mode in the test mode,

the test result data corresponding to the plurality of test results respectively.

13. The semiconductor memory device according to claim 10, wherein

the multibit test circuit generates a determination result data for being applied to one of the plurality of terminals in response to the plurality of test results in the test mode, the determination result data indicating whether the plurality of test results are in agreement.

14. The semiconductor memory device according to claim 10, wherein

each of the memory cell groups includes spare memory cell, and

the data bus receives data from the spare memory cell in a corresponding one of the memory cell groups when an address signal indicates a defective memory cell.

15. The semiconductor memory device according to claim 10, wherein

the multibit test circuit includes:

a plurality of first logic circuits generating the plurality of test results respectively, and

a second logic circuit generation a determination result data for being applied to one of the plurality of terminals, the determination result data being responsive to the plurality of test results.

16. The semiconductor memory device according to claim 15, wherein

the plurality of first logic circuits each generates test result data in response to a corresponding one of the plurality of test results.

17. The semiconductor memory device according to claim 10, wherein

each of the plurality of data busses includes a data bus line pair;

and

the semniconductor memory device further comprises;

a precharge circuit for precharging the data bus line pair; and

a plurality of discharge circuits coupled to the data bus line pair,

each of the plurality of discharge circuits selectively discharging either one of the lines of the data bus line pair in response to data from the corresponding one of memory cell groups.

18. A semiconductor memory device comprising:

(a) a memory cell array;

(b) a plurality of data bus line pairs;

(c) a plurality of discharge circuit groups each including a plurality of discharge circuits provided corresponding to the plurality of data bus line pairs respectively,

at least one of the discharge circuits in a selected discharge circuit group selectively discharging either one of the lines of a corresponding one of the plurality of data bus line pairs in response to data from the memory cell array in a normal mode;

(d) a plurality of precharge circuits provided corresponding to the plurality of data bus line pairs respectively,

each of the plurality of precharge circuits provided in common to the plurality of discharge circuit groups and precharging a corresponding data bus line pair; and

(e) a multibit test circuit generating a test result indicating whether data transmitted by at least two predetermined data bus line pairs of the plurality of data bus line pairs are in agreement in a test mode,

the discharge circuits corresponding to an identical data bus line pair of the predetermined data bus line pairs and included in selected discharge circuit groups selectively discharging either one of the lines of the identical data bus line pair in response to data from the memory cell array in the test mode, respectively.

19. The semiconductor memory device according to claim 18, wherein

each of the plurality of discharge circuits included in a selected one of the plurality of discharge circuit groups selectively discharges either one of the lines of the corresponding one of the plurality of data bus line pairs in the normal mode, and

each of the plurality of discharge circuits included in the plurality of discharge circuit groups selectively discharges either one of the lines of the corresponding one of the plurality of data bus line pairs in the test mode.

24. The semiconductor memory device according to claim 18, wherein the multibit test circuit comprises:

a first stage determination circuit for generating a test result; and

a second stage determination circuit for generating a determination result data.

20. A semiconductor memory device comprising:

a memory cell array;

a plurality of data bus line pairs;

a plurality of discharge circuit groups each including a plurality of discharge circuits provided corresponding to said plurality of data bus line pairs respectively, each of the plurality of discharge circuits discharging either one of the lines of a corresponding one of said plurality of data bus line pairs in response to data applied to said each of the plurality of discharge circuits;

a plurality of amplifier groups provided corresponding to said plurality of discharge circuit groups respectively, each including a plurality of amplifiers corresponding to the plurality of discharge circuits included in a corresponding one of said plurality of discharge circuit groups, each of the plurality of amplifiers applying data to a corresponding one of the plurality of discharge circuits from said memory cell array when said each of the plurality of amplifiers is enabled, at least one of the plurality of amplifiers included in a selected one of said plurality of amplifier groups being enabled and the other amplifiers included in unselected amplifier groups being disabled in a normal mode, said plurality of amplifiers included in at least two of said plurality of amplifier groups being enabled in a test mode;

a plurality of precharge circuits provided corresponding to said plurality of data bus line pairs respectively, each for precharging a corresponding one of said plurality of data bus line pairs, each of said plurality of precharge circuits being provided in common to said plurality of discharge circuit groups; and

a multibit test circuit producing a test result indicating whether data transmitted by said plurality of data bus line pairs are in agreement in the test mode.

21. The semiconductor memory device according to claim 20, wherein

each of the plurality of amplifiers has first and second outputs complementary to each other,

each of the plurality of discharge circuits includes a first transistor coupled between one line of a corresponding data bus line pair and ground, and a second transistor coupled between another line of the corresponding data bus line pair and ground, the first and second transistors being responsive to the first and second outputs respectively.

22. A semiconductor memory device comprising:

a memory cell array;

a plurality of data bus line pairs;

a plurality of discharge circuits, at least two of said plurality of discharge circuits corresponding to each of said plurality of data bus line pairs, each of said plurality of discharge circuits discharging either one of the lines of a corresponding one of said plurality of data bus line pairs in response to data applied to each of said plurality of discharge circuits;

a plurality of amplifiers corresponding to said plurality of discharge circuits respectively, each of said plurality of amplifiers applying data to a corresponding one of said plurality of discharge circuits from said memory cell array when each of said plurality of amplifiers is enabled, one of the amplifiers being enabled and the other amplifiers being disabled in a normal mode, said one and other amplifiers being associated with one of said plurality of data bus line pairs, at least two of the amplifiers associated with each of said plurality of data bus line pairs being enabled in a test mode;

a plurality of precharge circuits provided corresponding to the plurality of data bus line pairs respectively, each for precharging a corresponding one of the plurality of data bus line pairs, each of said plurality of precharge circuits being provided in common to the discharge circuits corresponding to the corresponding one of said plurality of data bus line pairs; and

a multibit test circuit producing a test result indicating whether data transmitted by said plurality of data bus line pairs are in agreement in the test mode.

23. The semiconductor memory device according to claim 22, wherein

each of said plurality of amplifiers has first and second outputs complementary to each other,

each of said plurality of discharge circuits includes a first transistor coupled between one line of a corresponding data bus line pair and ground, and a second transistor coupled between another line of the corresponding data bus line pair and ground, the first and second transistors being responsive to the first and second outputs respectively.