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Method for forming copper damascene structures by using a dual CMP barrier layer

  • US 6,004,188 A
  • Filed: 09/10/1998
  • Issued: 12/21/1999
  • Est. Priority Date: 09/10/1998
  • Status: Expired due to Term
First Claim
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1. A method of forming conducting metal lines and interconnects (studs) in trenches and vias in the fabrication of integrated circuit devices that forms CMP planarized structure without dishing comprising:

  • providing a substrate having an insulator layer deposited upon said substrate;

    depositing a layer of first material upon the insulator layer;

    providing patterning and etching of the first material and insulator layer to form via holes for interconnects;

    providing patterning and etching of the first material and insulator layer to form trenches for conducting lines;

    blanket depositing a conformal layer of second material above the patterned layer of the first material and insulator layer;

    providing with the second material a covering or lining of the trench and via structures;

    depositing a blanket conducting metal over the entire substrate filling the open trench and via structures;

    chemical-mechanical polishing the conducting metal layer in a two-step process;

    a first step of polishing back both top metal layer with the second material layer, said second material layer being harder than the conducting metal;

    further chemical-mechanical polishing back both top metal layer with the first material layer, said first material layer being soft material and close to the conducting metal in polishing rate, to form planarized conducting metal line and interconnect structures, without dishing; and

    removing in said two step process all the residual first material and leaving second layer material as a liner and diffusion barrier in the trench/via structures.

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