Method for forming copper damascene structures by using a dual CMP barrier layer

• US 6,004,188 A
• Filed: 09/10/1998
• Issued: 12/21/1999
• Est. Priority Date: 09/10/1998
• Status: Expired due to Term

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Inventors: Roy, Sudipto Ranendra
• Primary Examiner(s): Scherbel, David A.
• Assistant Examiner(s): OJINI, EZIAMARA ANTHONY
• Application Number:
  US09/151,153
• Time in Patent Office: 467 Days
• Field of Search: 451/37, 451/41, 451/57, 451/59, 451/53, 451/28, 451/29, 451/285, 451/286, 451/287, 451/289
• US Class Current: 451/41
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation

Abstract

An improved and new method for forming dual damascene CMP of copper lines and interconnects(studs) using a dual CMP barrier layer. The two layer polishing barrier produces planar copper structures and solves dishing problems caused when the soft exhibits to a high polishing rate relative to the surround material. The polishing barrier layers consist of bottom layer of TiN with a layer of Ta or TaN on top of TiN layer. The top layer has a low polishing and the bottom layer has high polishing similar to the polishing of copper. Dishing of the copper lines and interconnects is avoided by the method. The result is better uniformity across the substrate and better electrical performance due to the increased copper line cross-sectional.

Claims

1. A method of forming conducting metal lines and interconnects (studs) in trenches and vias in the fabrication of integrated circuit devices that forms CMP planarized structure without dishing comprising:

providing a substrate having an insulator layer deposited upon said substrate;

depositing a layer of first material upon the insulator layer;

providing patterning and etching of the first material and insulator layer to form via holes for interconnects;

providing patterning and etching of the first material and insulator layer to form trenches for conducting lines;

blanket depositing a conformal layer of second material above the patterned layer of the first material and insulator layer;

providing with the second material a covering or lining of the trench and via structures;

depositing a blanket conducting metal over the entire substrate filling the open trench and via structures;

chemical-mechanical polishing the conducting metal layer in a two-step process;

a first step of polishing back both top metal layer with the second material layer, said second material layer being harder than the conducting metal;

further chemical-mechanical polishing back both top metal layer with the first material layer, said first material layer being soft material and close to the conducting metal in polishing rate, to form planarized conducting metal line and interconnect structures, without dishing; and

removing in said two step process all the residual first material and leaving second layer material as a liner and diffusion barrier in the trench/via structures.

2. The method of claim 1, wherein said insulating oxide layer is silicon oxide, deposited by the method of PE deposited TEOS oxide in the thickness range from 4,000 Å

to 12,000 Å

.

3. The method of claim 1, wherein said layer of first material is TiN, deposited by PVD in a thickness range from 300 Å

to 1,000 Å

.

4. The method of claim 1, wherein said layer of second material is Ta/TaN, deposited by PVD in a thickness range from 200 Å

to 500 Å

.

5. The method of claim 1, wherein said layer of top conducting metal is copper, deposited by CVD in a thickness range from 10,000 Å

to 30,000 Å

.

6. The method of claim 1, wherein said thin films of TiN, Ta, and TaN are deposited by CVD.

7. A method of claim 1, wherein TiN layer polishing properties have a faster removal rate than Ta or TaN.

8. The method of claim 1, wherein the material Ta or TaN has a slower polishing rate than copper.

9. The method of claim 1, wherein TiN forms a buffer layer for Ta or TaN.

10. The method of claim 1, wherein a combination of Ta/TaN forms a dual layer with TiN and acts as a polishing barrier to yield planar copper structures.

11. The method of claim 1, using the dual layers of TiN, Ta/TaN in a damascene process that planarizes Cu lines and interconnects using CMP, with built-in polishing stop at the insulating material surface.

12. The method of claim 1, wherein the dual layers combined action:

TiN polishing being close that of Cu, Ta or TaN a harder material and polishes at slower rate than the soft copper, planarize the surface.

13. A method of using the dual damascene technique to form, a conductive contact to a semiconductor diffusion and interconnection wiring pattern, in the fabrication of an MOSFET that form CMP planarized structures without dishing comprising:

providing said active device element in an semiconductor substrate;

providing a semiconductor substrate having an insulator layer deposited upon said semiconductor substrate;

depositing a layer of first material upon the insulator layer;

providing patterning and etching of the first material and insulator layer to form via holes for interconnects;

providing patterning and etching of the first material and insulator layer to form trenches for conducting lines;

blanket depositing a conformal layer of second material above the patterned layer of the first material and insulator layer;

providing with the second material a covering or lining of the trench and via structures;

depositing a blanket conducting metal over the entire substrate filling the open trench and via structures;

chemical-mechanical polishing the conducting metal layer in a two-step process;

a first step of polishing back both top metal layer with the second material layer, said second material layer being harder than the conducting metal;

further chemical-mechanical polishing back both top metal layer with the first material layer, said first material layer being soft material and close to the conducting metal in polishing rate, to form planarized conducting metal line and interconnect structures, without dishing; and

removing in said two-step process all the residual first material and leaving second layer material as a liner and diffusion barrier in the trench and semiconductor diffusion contact area.

14. The method of claim 13, wherein the contact is made to a diffusion area of an MOSFET on a semiconductor substrate.

15. A method of using a dual damascene technique to form a conductive contact to a multi-level metal line and interconnection wiring pattern, in the fabrication semiconductor devices that forms CMP planarize structures without dishing comprising:

providing said conducting line on an interlevel dielectric, which is on a semiconductor substrate;

depositing an insulator layer upon the conducting line;

depositing a layer of first material upon the insulator layer;

providing patterning and etching of the first material and insulator layer to form via holes for interconnects;

providing patterning and etching of the first material and insulator layer to form trenches for conducting lines;

blanket depositing a conformal layer of second material above the patterned layer of the first material and insulator layer, and thus;

providing with the second material a covering or lining of the trench and via structures;

depositing a blanket conducting metal over the entire substrate filling the open trench and via structures;

chemical-mechanical polishing the conducting metal layer in a two-step process;

a first step of polishing back both top metal layer with the second material layer, said second material layer being harder than the conducting metal;

further chemical-mechanical polishing back both top metal layer with the first material layer, said first material layer being soft material and close to the conducting metal in polishing rate, to form planarized conducting metal line and interconnect structures, without dishing;

removing in said two-step process all the residual first material and leaving second layer material as a liner and diffusion barrier in the trench and interconnect structure.

16. The method of claim 15, wherein a dual damascene process with dual layer CMP barrier layer is used, contact is made to a conducting line in a multi-level metal connection structure on a semi-conductor substrate.