Process for manufacturing printed circuit boards

• US 6,004,619 A
• Filed: 11/07/1997
• Issued: 12/21/1999
• Est. Priority Date: 11/07/1996
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Olbrich, Walter, Dippon, Siegfrid
• Primary Examiner(s): Talbot, Brian K.
• Application Number:
  US08/965,853
• Time in Patent Office: 774 Days
• Field of Search: 427/97, 427/99, 427/124, 427/282, 427/300, 427/554, 427/405
• US Class Current: 29/852
• CPC Class Codes: H05K 2201/0376 Flush conductors, i.e. flush with the surface of the printed circuit
• CPC Class Codes: H05K 2201/09036 Recesses or grooves in insulating substrate
• CPC Class Codes: H05K 3/0032 of organic insulating material
• CPC Class Codes: H05K 3/048 using a lift-off resist pattern or a release layer pattern
• CPC Class Codes: H05K 3/107 by filling grooves in the support with conductive material H05K3/045, H05K3/101, H05K3/1258 and H05K3/465 take precedence
• CPC Class Codes: H05K 3/143 Masks therefor H05K3/048 takes precedence
• CPC Class Codes: H05K 3/146 By vapour deposition
• CPC Class Codes: H05K 3/388 by the use of a metallic or inorganic thin film adhesion layer
• CPC Class Codes: H05K 3/426 initial plating of through-holes in substrates without metal
• CPC Class Codes: H05K 3/428 initial plating of through-holes in substrates having a metal pattern
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base

Abstract

Process for manufacturing circuit boards in which a masking layer (2) is applied to a carrier substrate (1) of insulating material and after producing openings for soldering pads, conductor traces, and through or blind holes, in accordance with a preferred embodiment by laser ablation, a thin electrically conductive layer (5) is applied to the surface of the carrier substrate including the masking layer. Subsequently, the masking layer (2) and the conductive layer deposited thereon, for example copper, are removed and the remaining metal surfaces (6) are chemically reinforced to produce the desired thickness. The process permits the production of dense structures using few process steps and without additional abrasion steps.

Claims

1. Process of manufacturing printed circuit boards, comprising the following steps:

a) applying a masking layer to an insulating carrier substrate,

b) then producing recesses in the masking layer and in an upper region of the carrier substrate for at least one of (i) soldering pads, (ii) conductor traces and (iii) through holes in the masking layer and the carrier substrate,

c) then applying a conductive layer to the surface of the carrier substrate while the masking layer is in situ on the carrier substrate so that the conductive layer is applied to the masking layer and recesses,

d) then removing the masking layer with the conductive layer applied thereon without removing the conductive layer from the recesses so that a residual portion of the conductive layer remains in the recesses, and

e) then applying metal to the residual portion of the conductive layer to attain a thicker residual portion.

2. Process in accordance with claim 1, characterized in that, to produce a multi-layer circuit board, a carrier substrate is laminated onto at least one side of a standard circuit board or the circuit board produced in accordance with claim 1, and process steps a) through e) are carried out.

3. Process in accordance with claim 1, characterized in that the recessed structures are produced by laser ablation.

4. Process in accordance with claim 1, characterized in that the recesses in the upper region of the carrier substrate in accordance with step b) have a depth of approximately 20 μ

m.

5. Process in accordance with claim 1, characterized in that application of the conductive layer is performed by physical vapor deposition or plasma enhanced vapor deposition processes.

6. Process in accordance with claim 2, characterized in that the recessed structures are produced by laser ablation.

7. Process in accordance with claim 6, characterized in that the structure depth in the upper region of the carrier substrate in accordance with step b) is approximately 20 μ

m.

8. Process in accordance with claim 7, characterized in that application of the conductive layer is performed by physical vapor deposition or plasma enhanced vapor deposition processes.

9. Process in accordance with claim 1, wherein the conductive layer is applied, the masking layer is removed and the metal is applied to the residual portion of the conductive layer so that all exposed portions of the soldering pads of through holes and the conductor traces remaining on the carrier substrate after the masking layer has been removed are substantially coplanar.