Integrated circuit processing

• US 6,004,827 A
• Filed: 09/03/1997
• Issued: 12/21/1999
• Est. Priority Date: 09/03/1997
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Ryan, Vivian Wanda
• Primary Examiner(s): DUTTON, BRIAN KEITH
• Application Number:
  US08/922,487
• Time in Patent Office: 839 Days
• Field of Search: 438/6, 438/10, 438/11, 438/14, 438/17, 438/18
• US Class Current: 438/6
• CPC Class Codes: H01L 22/24 Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change voltage contrast G01R31/311
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

A variety of test structures may be fabricated with aluminum runners and overlying dielectrics. The dielectrics are removed and bumps are observed upon the aluminum runners. Unevenness in the bump distribution is a predictor of long term reliability problems. A test structure may be utilized to design integrated mass production fabrication processes.

Claims

1. A method comprising:

forming a metal runner overlying a substrate;

forming a material layer in contact with at least a portion of said metal runner;

removing said material layer from said metal runner thereby leaving bumps upon said metal runner;

measuring the density of said bumps.

2. The method claim 1 in which said metal is predominantly tungsten.

3. The method of claim 1 in which said metal is predominantly aluminum.

4. The method of claim 1 in which said metal is predominantly copper.

5. The method of claim 1 in which said material layer is an oxide of silicon.

6. The method of claim 5 in which said material layer is formed from TEOS.

7. A method of manufacturing an integrated circuit, the method comprising:

forming a plurality of test samples, each of said test samples having a substrate with at least one metal runner formed thereover and each of said test samples being formed by a respective set of process parameters;

forming a material layer in contact with at least a portion of each of said at least one metal runners;

removing said material layer from each of said at least one metal runners thereby leaving bumps on each of said at least one metal runners said bumps having a density and density gradient;

measuring said density or said density gradient of said bumps on each of said at least one metal runners;

choosing at least one of said plurality of test samples having said bump density or said bump density gradient which meets a predetermined criteria; and

selecting said respective process parameters of said chosen at least one of said plurality of test samples to manufacture the integrated circuit.

8. The method of claim 7 in which at least one of said respective process parameters is chosen from the group consisting of:

metal deposition temperature;

metal thickness;

etching recipe;

runner geometry;

dopant concentration of dielectric;

sputter target composition;

sinter recipe; and

temperature ramp rate.