Semiconductor nonvolatile memory device and method of production of same

• US 6,005,270 A
• Filed: 11/09/1998
• Issued: 12/21/1999
• Est. Priority Date: 11/10/1997
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Noguchi, Takashi
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US09/188,233
• Time in Patent Office: 407 Days
• Field of Search: 257/20, 257/30, 257/43, 257/315, 257/316, 257/321, 257/337, 257/390, 257/401
• US Class Current: 257/315
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/48 with a tunnel dielectric layer also being used as part of the peripheral transistor

Abstract

A semiconductor nonvolatile memory device capable of lowering an operation voltage such as an erase voltage and capable of lowering costs and a method of production of the same, wherein a thin film transistor acting as the memory transistor is formed with a semiconductor layer 31b having a channel formation region formed on an insulating substrate 10 made of glass or plastic, a charge storing layer 32a formed on the semiconductor layer, a control gate 33a formed above the charge storing layer, and source and drain regions formed connected to the channel formation region.

Claims

1. A semiconductor nonvolatile memory device in which memory transistors having charge storing layers are connected,

said semiconductor nonvolatile memory device formed with a plurality of thin film transistors, each transistor comprising

a semiconductor layer having a channel formation region formed in an insulating substrate of glass or plastic,

a charge storing layer formed in the semiconductor layer,

a control gate formed at an upper layer of the charge storing layer, and

source and drain regions formed in the semiconductor layer and connected to the channel formation region,

each thin film transistor acting as a memory transistor.

2. A semiconductor nonvolatile memory device as set forth in claim 1, wherein said charge storing layer is a floating gate comprised of a conductor insulated by an insulating film.

3. A semiconductor nonvolatile memory device as set forth in claim 2, wherein said memory transistors are connected in a NOR type array.

4. A semiconductor nonvolatile memory device as set forth in claim 2, wherein said memory transistors are connected in a NAND type array.

5. A semiconductor nonvolatile memory device as set forth in claim 4, wherein each of the memory transistors comprises

a lower gate insulating film formed at a lower layer of the semiconductor layer and

an erase gate formed at a lower layer of the lower gate insulating film.

6. A semiconductor nonvolatile memory device as set forth in claim 5, wherein said erase gate is formed connected to at least an erase gate of an adjoining memory transistor.

7. A semiconductor nonvolatile memory device as set forth in claim 1, wherein said charging storing layer is an insulator having charge traps.

8. A semiconductor nonvolatile memory device as set forth in claim 7, wherein said insulator having charge traps is an oxide-nitride-oxide stacked insulating film or a nitride-oxide stacked insulating film.

9. A semiconductor nonvolatile memory device as set forth in claim 7, wherein said insulator having charge traps is an insulator holding internally nanocrystals comprised of conductors having an average particle size of 2 to 5 nm.

10. A semiconductor nonvolatile memory device as set forth in claim 7, wherein said memory transistors are connected in a NOR type array.

11. A semiconductor nonvolatile memory device as set forth in claim 7, wherein said memory transistors are connected in a NAND type array.

12. A semiconductor nonvolatile memory device as set forth in claim 11, wherein each of the memory transistors comprises

a lower gate insulating film formed at a lower layer of the semiconductor layer and

an erase gate formed at a lower layer of the lower gate insulating film.

13. A semiconductor nonvolatile memory device as set forth in claim 12, wherein said erase gate is formed connected to at least an erase gate of an adjoining memory transistor.

14. A semiconductor nonvolatile memory device as set forth in claim 1, wherein said semiconductor layer is formed by polycrystalline silicon or quasi single crystal silicon.

15. A semiconductor nonvolatile memory device as set forth in claim 14, wherein said substrate has a peripheral circuit transistor.

16. A semiconductor nonvolatile memory device as set forth in claim 15, wherein a gate width of a gate of the peripheral circuit transistor is larger than the gate length of the gate and the average particle size of the polycrystalline silicon or quasi single crystal silicon forming the semiconductor layer.

17. A semiconductor nonvolatile memory device as set forth in claim 14, wherein said charge storing layer is a floating gate comprised of a conductor insulated by an insulating film.

18. A semiconductor nonvolatile memory device as set forth in claim 17, wherein said memory transistors are connected in a NOR type array.

19. A semiconductor nonvolatile memory device as set forth in claim 17, wherein said memory transistors are connected in a NAND type array.

20. A semiconductor nonvolatile memory device as set forth in claim 19, wherein each of the memory transistors comprises

a lower gate insulating film formed at a lower layer of the semiconductor layer and

an erase gate formed at a lower layer of the lower gate insulating film.

21. A semiconductor nonvolatile memory device as set forth in claim 20, wherein said erase gate is formed connected to at least an erase gate of an adjoining memory transistor.

22. A semiconductor nonvolatile memory device as set forth in claim 14, wherein said charging storing layer is an insulator having charge traps.

23. A semiconductor nonvolatile memory device as set forth in claim 22, wherein said insulator having charge traps is an oxide-nitride-oxide stacked insulating film or a nitride-oxide stacked insulating film.

24. A semiconductor nonvolatile memory device as set forth in claim 22, wherein said insulator having charge traps is an insulator holding internally nanocrystals comprised of conductors having an average particle size of 2 to 5 nm.

25. A semiconductor nonvolatile memory device as set forth in claim 22, wherein said memory transistors are connected in a NOR type array.

26. A semiconductor nonvolatile memory device as set forth in claim 22, wherein said memory transistors are connected in a NAND type array.

27. A semiconductor nonvolatile memory device as set forth in claim 26, wherein each of the memory transistors comprises

a lower gate insulating film formed at a lower layer of the semiconductor layer and

an erase gate formed at a lower layer of the lower gate insulating film.

28. A semiconductor nonvolatile memory device as set forth in claim 27, wherein said erase gate is formed connected to at least an erase gate of an adjoining memory transistor.

29. A semiconductor nonvolatile memory device in which memory transistors having charge storing layers are connected,

said semiconductor nonvolatile memory device formed with a plurality of thin film transistors, each transistor comprising

a semiconductor layer formed by quasi single crystal silicon having a channel formation region formed in an insulating substrate of a silicon substrate covered on its surface with a silicon oxide film,

a charge storing layer formed in the semiconductor layer,

a control gate formed at an upper layer of the charge storing layer, and

source and drain regions formed in the semiconductor layer and connected to the channel formation region,

each thin film transistor acting as a memory transistor.

30. A semiconductor nonvolatile memory device as set forth in claim 29, wherein said substrate has a peripheral circuit transistor.

31. A semiconductor nonvolatile memory device as set forth in claim 30, wherein a gate width of a gate of the peripheral circuit transistor is larger than the gate length of the gate and the average particle size of the quasi single crystal silicon forming the semiconductor layer.

32. A semiconductor nonvolatile memory device as set forth in claim 29, wherein said charge storing layer is a floating gate comprised of a conductor insulated by an insulating film.

33. A semiconductor nonvolatile memory device as set forth in claim 32, wherein said memory transistors are connected in a NOR type array.

34. A semiconductor nonvolatile memory device as set forth in claim 32, wherein said memory transistors are connected in a NAND type array.

35. A semiconductor nonvolatile memory device as set forth in claim 34, wherein each of the memory transistors comprises

a lower gate insulating film formed at a lower layer of the semiconductor layer and

an erase gate formed at a lower layer of the lower gate insulating film.

36. A semiconductor nonvolatile memory device as set forth in claim 35, wherein said erase gate is formed connected to at least an erase gate of an adjoining memory transistor.

37. A semiconductor nonvolatile memory device as set forth in claim 29, wherein said charging storing layer is an insulator having charge traps.

38. A semiconductor nonvolatile memory device as set forth in claim 37, wherein said insulator having charge traps is an oxide-nitride-oxide stacked insulating film or a nitride-oxide stacked insulating film.

39. A semiconductor nonvolatile memory device as set forth in claim 37, wherein said insulator having charge traps is an insulator holding internally nanocrystals comprised of conductors having an average particle size of 2 to 5 nm.

40. A semiconductor nonvolatile memory device as set forth in claim 37, wherein said memory transistors are connected in a NOR type array.

41. A semiconductor nonvolatile memory device as set forth in claim 37, wherein said memory transistors are connected in a NAND type array.

42. A semiconductor nonvolatile memory device as set forth in claim 41, wherein each of the memory transistors comprises

a lower gate insulating film formed at a lower layer of the semiconductor layer and

an erase gate formed at a lower layer of the lower gate insulating film.

43. A semiconductor nonvolatile memory device as set forth in claim 42, wherein said erase gate is formed connected to at least an erase gate of an adjoining memory transistor.

44. A semiconductor nonvolatile memory device in which memory transistors having charge storing layers are connected,

said semiconductor nonvolatile memory device formed with a plurality of thin film transistors, each transistor comprising

a semiconductor layer formed by polycrystalline silicon having a channel formation region formed in an insulating substrate of a silicon substrate coated on its surface with a silicon oxide film,

a charge storing layer formed in the semiconductor layer,

a control gate formed at an upper layer of the charge storing layer, and

source and drain regions formed in the semiconductor layer and connected to the channel formation region,

each thin film transistor acting as a memory transistor,

the substrate comprising a peripheral circuit transistor,

the gate width of the gate of the peripheral circuit transistor being larger than the gate length of the gate and the average particle size of the polycrystalline silicon forming the semiconductor layer.

45. A semiconductor nonvolatile memory device as set forth in claim 44, wherein said charge storing layer is a floating gate comprised of a conductor insulated by an insulating film.

46. A semiconductor nonvolatile memory device as set forth in claim 45, wherein said memory transistors are connected in a NOR type array.

47. A semiconductor nonvolatile memory device as set forth in claim 45, wherein said memory transistors are connected in a NAND type array.

48. A semiconductor nonvolatile memory device as set forth in claim 47, wherein each of the memory transistors comprises

a lower gate insulating film formed at a lower layer of the semiconductor layer and

an erase gate formed at a lower layer of the lower gate insulating film.

49. A semiconductor nonvolatile memory device as set forth in claim 48, wherein said erase gate is formed connected to at least an erase gate of an adjoining memory transistor.

50. A semiconductor nonvolatile memory device as set forth in claim 44, wherein said charging storing layer is an insulator having charge traps.

51. A semiconductor nonvolatile memory device as set forth in claim 50, wherein said insulator having charge traps is an oxide-nitride-oxide stacked insulating film or a nitride-oxide stacked insulating film.

52. A semiconductor nonvolatile memory device as set forth in claim 50, wherein said insulator having charge traps is an insulator holding internally nanocrystals comprised of conductors having an average particle size of 2 to 5 nm.

53. A semiconductor nonvolatile memory device as set forth in claim 50, wherein said memory transistors are connected in a NOR type array.

54. A semiconductor nonvolatile memory device as set forth in claim 50, wherein said memory transistors are connected in a NAND type array.

55. A semiconductor nonvolatile memory device as set forth in claim 54, wherein each of the memory transistors comprises

a lower gate insulating film formed at a lower layer of the semiconductor layer and

an erase gate formed at a lower layer of the lower gate insulating film.

56. A semiconductor nonvolatile memory device as set forth in claim 55, wherein said erase gate is formed connected to at least an erase gate of an adjoining memory transistor.

57. A method of production of a semiconductor nonvolatile memory device in which memory transistors having charge storing layers are connected,

said method of production of a semiconductor nonvolatile memory device comprising forming a thin film transistor acting as a memory transistor by

a step of forming a semiconductor layer having a channel formation region on an insulating substrate of glass or plastic;

a step of forming a charge storing layer at an upper layer of the semiconductor layer;

a step of forming a control gate at an upper layer of the charge storing layer; and

a step of forming source and drain regions connected to the channel formation region.

58. A method of production of a semiconductor nonvolatile memory device as set forth in claim 57, wherein the steps from the step of forming the semiconductor layer are performed at not more than 600°

C.

59. A method of production of a semiconductor nonvolatile memory device as set forth in claim 57, wherein the step of forming the semiconductor layer includes a step of forming a silicon layer and a step of crystallizing the silicon layer by exciter laser annealing or low temperature solid phase crystallization.

60. A method of production of a semiconductor nonvolatile memory device as set forth in claim 59, wherein the step of forming the silicon layer is a step of formation by a CVD (chemical vapor deposition) method using Si₂ H₆ as a starting material.

61. A method of production of a semiconductor nonvolatile memory device as set forth in claim 60, wherein said CVD method is a low pressure CVD method or a plasma CVD method.

62. A method of production of a semiconductor nonvolatile memory device as set forth in claim 59, wherein the step of forming the silicon layer is a step of formation by a CVD (chemical vapor deposition) method using SiH₄ as a starting material.

63. A method of production of a semiconductor nonvolatile memory device as set forth in claim 62, wherein said CVD method is a low pressure CVD method or a plasma CVD method.

64. A method of production of a semiconductor nonvolatile memory device as set forth in claim 59, wherein the step of forming the silicon layer is a step of formation by a sputtering method.

65. A method of production of a semiconductor nonvolatile memory device as set forth in claim 57, wherein the step of forming the charge storing layer includes a step of forming a gate insulating film at an upper layer of the semiconductor layer, a step of forming a floating gate comprised of a conductor at an upper layer of the gate insulating film, and a step of forming an inter-layer insulating film at an upper layer of the floating gate.

66. A method of production of a semiconductor nonvolatile memory device as set forth in claim 65, wherein the memory transistors are formed connected in a NOR type array.

67. A method of production of a semiconductor nonvolatile memory device as set forth in claim 65, wherein the memory transistors are formed connected in a NAND type array.

68. A method of production of a semiconductor nonvolatile memory device as set forth in claim 67, which further comprises, before the step of forming the semiconductor layer, a step of forming an erase gate on the insulating substrate and a step of forming a lower gate insulating film on the erase gate.

69. A method of production of a semiconductor nonvolatile memory device as set forth in claim 57, wherein the step of forming the charge storing layer is a step of forming an insulator having charge traps at an upper layer of the semiconductor layer.

70. A method of production of a semiconductor nonvolatile memory device as set forth in claim 69, wherein the memory transistors are connected in a NOR type array.

71. A method of production of a semiconductor nonvolatile memory device as set forth in claim 69, wherein the memory transistors are formed connected in a NAND type array.

72. A method of production of a semiconductor nonvolatile memory device as set forth in claim 71, which further comprises, before the step of forming the semiconductor layer, a step of forming an erase gate on the insulating substrate and a step of forming a lower gate insulating film on the erase gate.

73. A method of production of a semiconductor nonvolatile memory device comprising a first transistor acting as a memory transistor having a charge storing layer and a second transistor for a peripheral circuit,

said method of production of a semiconductor nonvolatile memory device comprising:

a step of forming a first semiconductor layer having a first channel formation region for the first transistor in a first transistor forming region and forming a second semiconductor layer having a second channel formation region for the second transistor in a second transistor forming region on an insulating substrate of a silicon substrate coated on its surface with a silicon oxide film or on an insulating substrate of glass or plastic;

a step of forming a charge storing layer at an upper layer of the first semiconductor layer and forming a gate insulating film at an upper layer of the second semiconductor layer;

a step of forming a control gate at an upper layer of the charge storing layer and forming a gate electrode at an upper layer of the gate insulating film; and

a step of forming first source and drain regions connected to a first channel formation region and second source and drain regions connected to a second channel formation region.

74. A method of production of a semiconductor nonvolatile memory device as set forth in claim 73, wherein the step of forming the charge storing layer at an upper layer of the first semiconductor layer includes a step of forming a tunnel insulating film at an upper layer of the first semiconductor layer, a step of forming a floating gate at an upper layer of the tunnel insulating film, and a step of forming an inter-layer insulating film at an upper layer of the floating gate.

75. A method of production of a semiconductor nonvolatile memory device as set forth in claim 73, wherein the step of forming the charge storing layer at an upper layer of the first semiconductor layer is a step of forming an insulator having charge traps at an upper layer of the first semiconductor layer.

76. A method of production of a semiconductor nonvolatile memory device comprising a first transistor having a charge storing layer and a second transistor for a peripheral circuit,

said method of production of a semiconductor nonvolatile memory device comprising:

a step of forming an erase gate in a first transistor forming region on an insulating substrate of a silicon substrate coated on its surface with a silicon oxide film or on an insulating substrate of glass or plastic;

a step of forming a lower gate insulating film at an upper layer of the erase gate;

a step of forming a first semiconductor layer having a first channel formation region for the first transistor at an upper layer of the lower gate insulating film and forming a second semiconductor layer having a second channel formation region for the second transistor in a second transistor forming region on the substrate;

a step of forming a charge storing layer at an upper layer of the first semiconductor layer and forming a gate insulating film at an upper layer of the second semiconductor layer;

a step of forming a control gate at an upper layer of the charge storing layer and forming a gate electrode at an upper layer of the gate insulating film; and

a step of forming first source and drain regions connected to the first channel formation region and second source and drain regions connected to the second channel formation region.