Transistors having controlled conductive spacers, uses of such transistors and methods of making such transistors

• US 6,005,273 A
• Filed: 12/10/1997
• Issued: 12/21/1999
• Est. Priority Date: 10/31/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kao, David, Gonzalez, Fernando
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US08/987,819
• Time in Patent Office: 741 Days
• Field of Search: 257/296, 257/344, 257/365-367
• US Class Current: 257/366
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28132 conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

A transistor structure includes an insulated conductive gate spacer or a conductive layer under a nonconductive spacer, together forming a composite spacer, which contacted and driven separately from the conventional gate of the transistor. The gate spacer, conductive layer of a composite spacer or a portion or portions thereof serve as a control or controls for the transistors taking the form of a second gate or second and third gates for the transistors. The transistors may be used throughout an integrated circuit or it may be preferred to use the improved transistor only in critical speed paths of an integrated circuit. Delays within circuits including the improved transistors are reduced since the drain voltage can be higher than VCC and the BVDSS and subthreshold voltage are substantially higher than standard LDD transistors. When the improved transistors are used selectively within an integrated circuit, the remaining devices can be structured as standard LDD transistors, using the gate spacers in a conventional manner, and/or as conventional transistors.

Claims

1. A transistor structure comprising:

a gate structure formed on a first oxide layer on a semiconductor structure;

a secondary oxide layer formed on said gate structure;

a conductive spacer formed around said gate structure on said secondary oxide layer, said conductive spacer including an aperture over a portion of said gate structure;

a first contact to said gate structure by way of said aperture; and

a second contact to said conductive spacer.

2. A dual gate transistor structure comprising:

a gate structure formed on a first oxide layer on a semiconductor structure and defining a first gate;

a secondary oxide layer formed over said gate structure;

a conductive spacer formed around said gate structure on said secondary oxide layer, said conductive spacer defining a second gate and including an aperture over a portion of said gate structure;

a first contact to a portion of said gate structure corresponding to said aperture; and

a second contact to said conductive spacer.

3. A transistor structure comprising:

an actual gate and a pseudo gate formed on a first oxide layer on a semiconductor structure, said actual and pseudo gates being separated from one another;

a secondary oxide layer formed over said actual and pseudo gates;

a conductive spacer formed around said actual and pseudo gates on said secondary oxide layer, said conductive spacer including an aperture over a portion of said actual gate;

a first contact to a portion of said actual gate corresponding to said aperture; and

a second contact to said conductive spacer at said pseudo gate.

4. An integrated circuit structure comprising:

a first plurality of conventional LDD transistors; and

a second plurality of transistors each comprising;

a gate structure formed on a first oxide layer on a semiconductor structure;

a secondary oxide layer formed on said gate structure;

a conductive spacer formed around said gate structure on said secondary oxide layer, said conductive spacer including an aperture over a portion of said gate structure;

a first contact to said gate structure at a portion of said gate structure corresponding to said aperture; and

a second contact to said conductive spacer, said first plurality of conventional LDD transistors and said second plurality of transistors being interconnected to form said integrated circuit structure.

5. An integrated circuit structure as claimed in claim 4 wherein said integrated circuit structure includes output drivers comprising at least a portion of said second plurality of transistors.

6. A transistor structure comprising:

a gate structure formed on a first oxide layer on a semiconductor structure;

a secondary oxide layer formed on said gate structure;

a conductive layer formed around said gate structure on said secondary oxide layer, said conductive layer including an aperture over a portion of said gate structure;

a nonconductive spacer formed over said conductive layer, said nonconductive spacer including an aperture at least partially aligned with said aperture through said conductive layer;

a first contact to said gate structure at a portion of said gate structure corresponding to said apertures; and

a second contact to said conductive layer.

7. A dual gate transistor structure comprising:

a gate structure formed on a first oxide layer on a semiconductor structure and defining a first gate;

a secondary oxide layer formed over said gate structure;

a conductive layer formed on said secondary oxide on said gate structure, said conductive layer defining a second gate and including an aperture over a portion of said gate structure;

a nonconductive spacer formed over said conductive layer, said nonconductive spacer including an aperture at least partially aligned with said aperture through said conductive layer;

a first contact to said first gate at a portion of said gate structure corresponding to said apertures; and

a second contact to said conductive layer.

8. A transistor structure comprising:

a gate structure formed on a first oxide layer on a semiconductor structure;

a secondary oxide layer formed on said gate structure;

a conductive layer formed on said secondary oxide layer on said gate structure, said conductive layer including an aperture over a portion of said gate structure and forming a first conductive portion of a spacer;

a nonconductive layer formed over said conductive layer, said nonconductive layer including an aperture at least partially aligned with said aperture through said conductive layer and forming a second nonconductive portion of said spacer;

a first contact to said gate structure at a portion of said gate structure corresponding to said apertures; and

a second contact to said conductive layer.

9. A transistor structure comprising:

a gate structure formed on a first oxide layer on a semiconductor structure;

a secondary oxide layer formed on said gate structure;

a composite spacer formed on said secondary oxide layer on said gate structure, said composite spacer comprising a conductive layer formed over said gate structure and a nonconductive layer formed over said conductive layer, said composite spacer including an aperture over a portion of said gate structure;

a first contact to said gate structure by way of a portion of said gate structure corresponding to said aperture; and

a second contact to said conductive layer of said composite spacer.

10. An integrated circuit structure comprising:

a first plurality of conventional transistors;

a second plurality of transistors each comprising;

a gate structure formed on a first oxide layer on a semiconductor structure;

a secondary oxide layer formed on said gate structure;

a spacer formed on at least one side of said gate structure on said secondary oxide layer, at least a portion of said spacer adjacent to said secondary oxide layer being conductive and defining at least a second gate;

a first contact to said gate structure;

at least a second contact to said conductive portion of said spacer, said first plurality of conventional transistors and said second plurality of transistors being interconnected to form said integrated circuit structure; and

a third plurality of conventional LDD transistors, said third plurality of conventional LDD transistors being interconnected to said first plurality of said conventional transistors to form said integrated circuit structure.

11. An integrated circuit structure as claimed in claim 10 wherein said third plurality of conventional LDD transistors are interconnected to said second plurality of transistors to form said integrated circuit structure.

12. An integrated circuit structure comprising:

a first plurality of conventional transistors;

a second plurality of transistors each comprising;

a gate structure formed on a first oxide layer on a semiconductor structure;

a secondary oxide layer formed on said gate structure;

a spacer formed on at least one side of said gate structure on said secondary oxide layer, at least a portion of said spacer adjacent to said secondary oxide layer being conductive and defining at least a second gate;

a first contact to said gate structure;

at least a second contact to said conductive portion of said spacer, said first plurality of conventional transistors and said second plurality of transistors being interconnected to form said integrated circuit structure; and

a third plurality of conventional LDD transistors, said third plurality of conventional LDD transistors being interconnected to said second plurality of transistors to form said integrated circuit structure.