Low power consuming logic circuit

• US 6,005,418 A
• Filed: 12/11/1996
• Issued: 12/21/1999
• Est. Priority Date: 09/07/1995
• Status: Expired due to Fees

• Current Assignee: Yugen Kaisha Okid
• Original Assignee: Yugen Kaisha Okid
• Inventors: Taki, Kazuo
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US08/763,743
• Time in Patent Office: 1,105 Days
• Field of Search: 326/113, 326/121, 326/95, 326/98, 326/28, 326/83, 326/86, 327/389, 327/391
• US Class Current: 326/113
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence

Abstract

Disclosed is a low power consuming logic circuit to restrain a short circuit current which flows within an inverter circuit of an inverter having a clock input connected behind a pass-transistor logic circuit. In the logic circuit, the inverter having a clock input is provided on the output of a pass-transistor logic circuit. The inverter having a clock input includes the inverter circuit and write control means. A data holding circuit is connected to the output of the write control means. In the logic circuit, a clock is input to the inverter having a clock input after the output of the pass-transistor logic circuit is stabilized. Thus, the short circuit current which flows in the inverter circuit is restrained. In addition to the logic circuit, a positive feedback circuit for supplying an inverted signal from the inverter circuit to the output of the inverter having a clock input can be provided. In the logic circuit, the positive feedback circuit functions to further increase the voltage of the output signal of the pass-transistor logic circuit if it is higher than the input threshold of the inverter, and to further reduce the same voltage if it is lower than the input threshold of the inverter. Consequently, the short circuit current flows in the inverter having a clock input in a very short time.

Claims

1. A low power consuming logic circuit comprising:

a pass-transistor logic circuit having MOS type pass-transistors interconnected;

an inverter having a clock input connected to the output of said pass-transistor logic circuit; and

a data holding circuit connected to the output of said inverter having a clock input;

wherein a clock which is input to said inverter having a clock input is used both as an enabling inverter function of said inverter having a clock input and as a write control signal to said data holding circuit.

2. The low power consuming logic circuit according to claim 1, wherein the inverter having a clock input includes:

a PMOS transistor and an NMOS transistor which are connected to the output of the pass-transistor logic circuit and function as an inverter; and

write control means which is provided between said PMOS transistor and said NMOS transistor and has a PMOS output enable transistor and an NMOS output enable transistor,

wherein the outputs of said PMOS output enable transistor and said NMOS output enable transistor are connected as the output of said inverter having a clock input, and

the output of the pass-transistor logic circuit is inverted and output as the output of said inverter having a clock input to the data holding circuit when an inverted clock is input to the PMOS output enable transistor and a non-inverted clock is input to the NMOS output enable transistor.

3. The low power consuming logic circuit according to claim 1, wherein the inverter having a clock input includes:

a PMOS transistor and an NMOS transistor which are connected to the output of said pass-transistor logic circuit and function as an inverter; and

write control means having a first NMOS output enable transistor provided between said PMOS transistor and said NMOS transistor, and a second NMOS output enable transistor connected to the output of said PMOS transistor and the output of said first NMOS output enable transistor,

wherein the outputs of said second NMOS output enable transistor and said first NMOS output enable transistor are connected as the output of said inverter having a clock input, and

the output of said pass-transistor logic circuit is inverted and output as the output of said inverter having a clock input to said data holding circuit when a non-inverted clock is input to said first NMOS output enable transistor and said second NMOS output enable transistor.

7. The low power consuming logic circuit according to claim 2, further comprising a positive feedback circuit for supplying an inverted signal to the input of the inverter having a clock input on the basis of the output of said PMOS transistor and the output of said NMOS transistor of said inverter having a clock input.

8. The low power consuming logic circuit according to claim 7, wherein the outputs of said PMOS output enable transistor and said NMOS output enable transistor are connected to said positive feedback circuit, and

the output of the pass-transistor logic circuit is inverted and output as the output of the inverter having a clock input to said positive feedback circuit when an inverted clock is input to said PMOS output enable transistor and a non-inverted clock is input to said NMOS output enable transistor.

9. The low power consuming logic circuit according to claim 3, further comprising a positive feedback circuit for supplying an inverted signal to the input of the inverter having a clock input on the basis of the output of said PMOS transistor and the output of said NMOS transistor of said inverter having a clock input.

10. The low power consuming logic circuit according to claim 7, wherein the outputs of said PMOS transistor and said first NMOS output enable transistor are connected to said positive feedback circuit, and

the output of the pass-transistor logic circuit is inverted and output as the output of the inverter having a clock input to said positive feedback circuit when a non-inverted clock is input to the first NMOS output enable transistor and the second NMOS output enable transistor.

4. A low power consuming logic circuit comprising:

a pass-transistor logic circuit having MOS type pass-transistors interconnected;

an inverter having a clock input which is connected to said output of the pass-transistor logic circuit and has a plurality of outputs; and

a plurality of data holding circuits connected to said plurality of outputs of the inverter having a clock input, respectively,

wherein a clock which is input to said inverter having a clock input is used as a write control signal sent from the plurality of outputs of said inverter having a clock input to said plurality of data holding circuits.

5. The low power consuming logic circuit according to claim 4, wherein said inverter having a clock input includes:

a PMOS transistor and an NMOS transistor which are connected to the output of the pass-transistor logic circuit and function as an inverter; and

a plurality of write control means connected between the PMOS transistor and the NMOS transistor in parallel, each of which has a PMOS output enable transistor and an NMOS output enable transistor connected in series,

wherein the respective outputs of said PMOS output enable transistors and said NMOS output enable transistors of the respective write control means are connected as a plurality of outputs of said inverter having a clock input, and

the output of the pass-transistor logic circuit is inverted and output as the output of said inverter having a clock input to said data holding circuit when an inverted clock is input to said PMOS output enable transistor and a non-inverted clock is input to the NMOS output enable transistor in each of the write control means.

6. The low power consuming logic circuit according to claim 4, wherein the inverter having a clock input includes:

a PMOS transistor and an NMOS transistor which are connected to the output of the pass-transistor logic circuit and function as an inverter; and

a plurality of write control means, each having a first NMOS output enable transistor connected between the PMOS transistor and the NMOS transistor in parallel, and a second NMOS output enable transistor connected to the output of the PMOS transistor and that of the first NMOS output enable transistor,

wherein the outputs of the respective second NMOS output enable transistors are connected as the outputs of the inverter having a clock input, and

the output of the pass-transistor logic circuit is inverted and output as the output of the inverter having a clock input to the data holding circuit when a non-inverted clock is input to the first NMOS output enable transistor and the second NMOS output enable transistor in the write control means.

11. A low power consuming logic circuit, comprising;

a pass-transistor logic circuit having MOS type pass-transistors interconnected;

an inverter having a clock input which is connected to the output of the pass-transistor logic circuit and has a plurality of outputs;

a positive feedback circuit for inverting the output of said inverter having a clock input and outputting the inverted signal to the input of the inverter having a clock input; and

a plurality of data holding circuits connected to the plurality of outputs of the inverter having a clock input, respectively,

wherein a clock input to the inverter having a clock input is used as a write control signal for writing from the plurality of outputs of the inverter having a clock input to the plurality of data holding circuit, and

said clock input to the inverter having a clock input is used as feedback control signal for feedback from the output of said inverter having a clock input to the input of said inverter.

12. The low power consuming logic circuit according to claim 11, wherein the inverter having a clock input includes:

a PMOS transistor and an NMOS transistor which are connected to the outputs of the pass-transistor logic circuit and function as an inverter; and

a plurality of write control means connected between said PMOS transistor and said NMOS transistor in parallel, each of which has a PMOS output enable transistor and an NMOS output enable transistor connected in series,

wherein the output of said PMOS transistor and the output of said NMOS transistor are input to said positive feedback circuit,

the respective outputs of the PMOS output enable transistors and the NMOS output enable transistors in the respective write control means are connected to the respective data holding circuits, and

when an inverted clock is input to the PMOS output enable transistor and a non-inverted clock is input to the NMOS output enable transistor in the write control means, the output of said PMOS transistor and the output of said NMOS transistor are output as the output of said plurality of inverters having a clock input to the data holding circuits and are output to said positive feedback circuit.

13. The low power consuming logic circuit according to claim 11, wherein the inverter having a clock input includes:

a PMOS transistor and an NMOS transistor which are connected to the outputs of the pass-transistor logic circuit and function as an inverter; and

a plurality of write control means, each having a first NMOS output enable transistor connected between the PMOS transistor and the NMOS transistor in parallel, and a second NMOS output enable transistor connected to the output of the PMOS transistor and the output of the first NMOS output enable transistor,

wherein the output of the PMOS transistor and the output of the NMOS transistor are input to said positive feedback circuit,

the outputs of the respective second NMOS output enable transistors are connected to the respective data holding circuits, and

when a non-inverted clock is input to the first NMOS output enable transistor and the second NMOS output enable transistor in the write control means, the output of said PMOS transistor and the output of said NMOS transistor are output as the output of the inverter having a clock input to the data holding circuit and are output to said positive feedback circuit.