Low power consuming logic circuit
First Claim
1. A low power consuming logic circuit comprising:
- a pass-transistor logic circuit having MOS type pass-transistors interconnected;
an inverter having a clock input connected to the output of said pass-transistor logic circuit; and
a data holding circuit connected to the output of said inverter having a clock input;
wherein a clock which is input to said inverter having a clock input is used both as an enabling inverter function of said inverter having a clock input and as a write control signal to said data holding circuit.
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Accused Products
Abstract
Disclosed is a low power consuming logic circuit to restrain a short circuit current which flows within an inverter circuit of an inverter having a clock input connected behind a pass-transistor logic circuit. In the logic circuit, the inverter having a clock input is provided on the output of a pass-transistor logic circuit. The inverter having a clock input includes the inverter circuit and write control means. A data holding circuit is connected to the output of the write control means. In the logic circuit, a clock is input to the inverter having a clock input after the output of the pass-transistor logic circuit is stabilized. Thus, the short circuit current which flows in the inverter circuit is restrained. In addition to the logic circuit, a positive feedback circuit for supplying an inverted signal from the inverter circuit to the output of the inverter having a clock input can be provided. In the logic circuit, the positive feedback circuit functions to further increase the voltage of the output signal of the pass-transistor logic circuit if it is higher than the input threshold of the inverter, and to further reduce the same voltage if it is lower than the input threshold of the inverter. Consequently, the short circuit current flows in the inverter having a clock input in a very short time.
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Citations
13 Claims
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1. A low power consuming logic circuit comprising:
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a pass-transistor logic circuit having MOS type pass-transistors interconnected; an inverter having a clock input connected to the output of said pass-transistor logic circuit; and a data holding circuit connected to the output of said inverter having a clock input; wherein a clock which is input to said inverter having a clock input is used both as an enabling inverter function of said inverter having a clock input and as a write control signal to said data holding circuit. - View Dependent Claims (2, 3, 7, 8, 9, 10)
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4. A low power consuming logic circuit comprising:
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a pass-transistor logic circuit having MOS type pass-transistors interconnected; an inverter having a clock input which is connected to said output of the pass-transistor logic circuit and has a plurality of outputs; and a plurality of data holding circuits connected to said plurality of outputs of the inverter having a clock input, respectively, wherein a clock which is input to said inverter having a clock input is used as a write control signal sent from the plurality of outputs of said inverter having a clock input to said plurality of data holding circuits. - View Dependent Claims (5, 6)
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11. A low power consuming logic circuit, comprising;
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a pass-transistor logic circuit having MOS type pass-transistors interconnected; an inverter having a clock input which is connected to the output of the pass-transistor logic circuit and has a plurality of outputs; a positive feedback circuit for inverting the output of said inverter having a clock input and outputting the inverted signal to the input of the inverter having a clock input; and a plurality of data holding circuits connected to the plurality of outputs of the inverter having a clock input, respectively, wherein a clock input to the inverter having a clock input is used as a write control signal for writing from the plurality of outputs of the inverter having a clock input to the plurality of data holding circuit, and said clock input to the inverter having a clock input is used as feedback control signal for feedback from the output of said inverter having a clock input to the input of said inverter. - View Dependent Claims (12, 13)
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Specification