Integrated power switch for parasitically powered devices

• US 6,005,424 A
• Filed: 12/28/1995
• Issued: 12/21/1999
• Est. Priority Date: 12/28/1995
• Status: Expired due to Fees

• Current Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Original Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Douglass, James M.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): LE, DINH THANH
• Application Number:
  US08/583,139
• Time in Patent Office: 1,454 Days
• Field of Search: 327/544, 327/545, 327/525, 327/365, 327/142, 327/143, 327/442, 327/108, 327/374, 327/387, 327/388, 327/512, 327/198
• US Class Current: 327/143
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: H04L 25/02 Details ; arrangements for supplying electrical power along data transmission lines systems for transmitting signals via power distribution lines H04B3/54

Abstract

An integrated dynamic interconnect device for connecting and disconnecting at least a portion of a parasitically powered integrated electronic circuit, includes a power input, a power output, a signal input to receive a connect/disconnect signal, and an integrated switching mechanism which is responsive to the signal input receiving a connect/disconnect signal to electrically connect and disconnect the power input and the power output.

Claims

1. A dynamic switch for connecting and disconnecting an integrated electronic circuit from a power source, said dynamic switch comprising:

a power input for electrically connecting to the power source;

a power output for electrically connecting to said integrated electronic circuit;

a first signal input for receiving connect/disconnect signals;

a first means responsive to said first signal input receiving a connect/disconnect signal for electrically connecting and disconnecting said power input and said power output; and

said first means including a first inverter, a first NAND gate, and a second NAND gate, said first inverter having an input and an output, and each of said first NAND gate and said second NAND gate having first and second inputs, and an output, said input of said first inverter electrically connected to said first signal input, said output of said first inverter electrically connected to said second input of said first NAND gate, said first input of said first NAND gate electrically connected to the power source and said output of said first NAND gate electrically connected to said second input of said second NAND gate.

2. A dynamic switch as recited in claim 1, wherein:

said first means further includes a latch coupled between the power source and said first input of said first NAND gate, said latch having an input and an output, said input of said latch being electrically connected to the power source and said output being connected to said first input of said first NAND gate.

3. A dynamic switch as recited in claim 2, wherein:

said output of said latch is electrically connected to said first input of said second NAND gate.

4. A dynamic switch as recited in claim 3, wherein:

said first means further includes a second inverter having a input and an output, said output of said second NAND gate electrically connected to said input of said second inverter.

5. A dynamic switch as recited in claim 4, wherein:

said first means further includes a CMOS inverter having an input, an output, a positive voltage terminal and a negative voltage terminal; and

said input of said CMOS inverter being electrically connected to said output of said second inverter, said positive voltage terminal being electrically connected to the power source, said output of said CMOS inverter being electrically connected to said power output, and said negative voltage terminal being electrically connected to ground.

6. A dynamic switch as recited in claim 5, further comprising:

a second means connected between said power input and said power output for preventing the disconnection of said power input from said power output.

7. A dynamic switch as recited in claim 6, wherein:

said second means includes at least one fuse coupled to said power input and said power output.

8. A dynamic switch as recited in claim 2, wherein:

said latch includes a fuse.

9. In an integrated thermometer, a switching device for connecting and disconnecting at least a portion of the integrated thermometer, said switching device comprising:

a power input for receiving power from a power source;

a power output electrically connected to said at least a portion of the integrated thermometer;

a first signal input for receiving connect/disconnect signals;

a switching means, responsive to said first signal input receiving connect/disconnect signals, said switching means electrically connected between said power input and said power output for electrically connecting and disconnecting said at least a portion of the integrated thermometer from the power source;

said switching means including a first inverter having an input and an output, said input of said first inverter electrically connected to said first signal input; and

said switching means further including a first NAND gate and a second NAND gate, said each of said first and second NAND gates having a first and a second input and an output, said first input of said first NAND gate electrically connected to said power input, and said second input of said first NAND gate electrically connected to said output of said first inverter, and said output of said first NAND gate electrically connected to said second input of said second NAND gate.

10. A switching device as recited in claim 9, wherein:

said switching device further includes a latch having an input and an output, said input being electrically connected to the power source and said output being electrically connected to said first input of said first NAND gate.

11. A switching device as recited in claim 10, wherein:

said switching means further includes a second NAND gate having first and second inputs and an output; and

said output of said latch electrically connected to said first input of said second NAND gate and said output of said first NAND gate electrically connected to said second input of said second NAND gate.

12. A switching device as recited in claim 11, wherein:

said switching means further includes a second inverter having a input and an output, said output of said second NAND gate electrically connected to said input of said second inverter.

13. A switching device as recited in claim 12, wherein:

said switching means further includes a CMOS inverter having an input, an output, a positive voltage terminal and a negative voltage terminal; and

said input being electrically connected to said output of said second inverter, said positive voltage terminal being electrically connected to the power source, said output of said CMOS inverter being electrically connected to said power output, and said negative voltage terminal being electrically connected to ground.

14. A switching device as recited in claim 13, further comprising:

a bypass connecting means connected between said power input and said power output for preventing the disconnection of said at least a portion of said integrated thermometer.

15. A switching device as recited in claim 14, wherein:

said bypass connecting means includes at least one fuse electrically connecting said power input with said power output.

16. A switching device as recited in claim 15, wherein:

said bypass connecting means includes a fuse electrically connected between said latch and ground.