Operational amplifier

• US 6,005,440 A
• Filed: 07/23/1998
• Issued: 12/21/1999
• Est. Priority Date: 11/26/1997
• Status: Expired due to Fees

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Okamoto, Seiji
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Nguyen, Patricia T.
• Application Number:
  US09/120,846
• Time in Patent Office: 516 Days
• Field of Search: 330/253, 330/255, 330/292, 330/298
• US Class Current: 330/253
• CPC Class Codes: H03F 1/086 with FET's
• CPC Class Codes: H03F 1/523 for amplifiers using field-effect devices H03F1/526 takes precedence
• CPC Class Codes: H03F 3/3032 using two SEPP driving stages
• CPC Class Codes: H03F 3/4521 Complementary long tailed pairs having parallel inputs and being supplied in parallel
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

An operational amplifier capable of supplying a large power approximate to a power supply voltage to a load resistance and of rendering the current consumption relative to the power supply voltage small when a signal is not issued. The operational amplifier comprises a first differential amplifying stage, a first amplifying stage, a first level shifting stage, a second differential amplifying stage, a second amplifying stage, a second level shifting stage, and outputting stage, a first phase compensation circuit and a second compensation circuit. The first differential amplifying stage differentially amplifies input signals while n-channel transistors serves as a differential amplifying elements. The second differential amplifying stage differentially amplifies input signals while p-channel transistors serves as a differential amplifying elements. The first amplifying stage amplifies an output of the first differential amplifying stage in opposite phase. The second amplifying stage amplifies an output of the second differential amplifying stage in opposite phase. The outputting stage comprising a p-channel transistor a source of which is connected to a first power supply voltage and an n-channel transistor a source of which is connected to a second power supply voltage for executing complementary operation in response to outputs of the first and second differential amplifying stages. The first level shifting stage level shifts an output of the first amplifying stage in the direction of the first power supply voltage to control a gate of the n-channel transistor of the outputting stage. The second level shifting stage level shifts an output of the second amplifying stage in the direction of the second power supply voltage to control a gate of the p-channel transistor of the outputting stage.

Claims

1. An operational amplifier comprising;

a first differential amplifying stage for differentially amplifying input signals comprising n-channel MOS transistors serving as differential amplifying elements;

a second differential amplifying stage for differentially amplifying input signals comprising p-channel MOS transistors serving as differential amplifying elements;

a first amplifying stage for amplifying an output of the first differential amplifying stage in opposite phase;

a second amplifying stage for amplifying an output of the second differential amplifying stage in opposite phase;

an outputting stage comprising a p-channel transistor a source of which is connected to a first power supply voltage and an n-channel transistor a source of which is connected to a second power supply voltage for executing complementary operation in response to outputs of the first and second differential amplifying stages;

a first level shifting stage for level shifting an output of the first amplifying stage in the direction of the first power supply voltage to control a gate of the n-channel transistor of the outputting stage; and

a second level shifting stage for level shifting an output of the second amplifying stage in the direction of the second power supply voltage to control a gate of the p-channel transistor of the outputting stage.

2. The operational amplifier according to claim 1, wherein

respective first and second amplifying stages comprise transistors for amplifying purpose and constant current elements, and wherein

the transistor for amplifying purpose of the first differential amplifying stage having substantially the same characteristics as a load transistor of the first differential amplifying stage, and

the transistor for amplifying purpose of the second differential amplifying stage having substantially the same characteristics as a load transistor of the second differential amplifying stage.

3. The operational amplifier according to claim 1, wherein

output dc voltages of the first and second amplifying stages are set in the manner that the voltages between the sources and drains of transistors constituting the load elements of the first and second amplifying stages are lower than threshold voltages of the same transistors.

4. The operational amplifier according to claim 1, wherein

bias voltages of transistors for realizing respective constant current elements of the first differential amplifying stage, the second differential amplifying stage, the first amplifying stage, the second amplifying stage, the first level shifting stage and the second level shifting stage are produced by a bias circuit for receiving a reference power supply voltage.

5. The operational amplifier according to claim 1, wherein

the transistors for realizing constant current elements have substantially the same transistor characteristics as those for producing bias voltages by the bias circuit, and these transistors are connected to each other by mirror connection.

6. The operational amplifier according to claim 4, wherein

the bias circuit produces a first bias voltage for determining a current which flows through the constant current element constituted by the p-channel transistor and a second bias voltage for determining a current which flows through the constant current element constituted by the n-channel transistor, wherein

the first and the second bias voltages are determined by a single p-channel transistor or a single n-channel transistor and a reference power supply voltage.

7. The operational amplifier according to claim 1 further comprising:

a first power-down control transistor provided between the gate of the p-channel transistor of the outputting stage and the first power supply voltage; and

a second power-down control transistor provided between the gate of the n-channel transistor of the outputting stage and the second power supply voltage.

8. The operational amplifier according to claim 1 further comprising:

a first phase compensation circuit provided between an output terminal of the outputting stage and an output terminal of the second level shifting stage; and

a second phase compensation circuit provided between the output terminal of the outputting stage and the output terminal of the first level shifting stage.

9. The operational amplifier according to claim 1, wherein the first amplifying stage comprises:

a p-channel transistor having a source connected to the first supply voltage and a gate connected to the output terminal of the first differential amplifying stage, and

an n-channel transistor having a source connected to the second power supply voltage and a gate connected to a second bias voltage, and a drain connected to a drain of the p-channel transistor,

wherein the drain of the p-channel transistor serves as the output terminal.

10. The operational amplifier according to claim 1, wherein the second amplifying stage comprises;

an n-channel transistor having a source connected to the second power supply voltage and a gate connected to the output terminal of the second differential amplifying stage; and

a p-channel transistor having a source connected to the first power supply voltage and a gate connected to a first bias voltage, and a drain connected to a drain of the n-channel transistor;

wherein the drain of the n-channel transistor serves as the output terminal.

11. The operational amplifier according to claim 1, wherein the first level shifting stage comprises;

a p-channel transistor having a source connected to the first power supply voltage and a gate connected to a first bias voltage; and

an n-channel transistor having a source connected to the output terminal of the first amplifying stage, a gate and a drain commonly connected to each other to form a common node connected to a drain of the p-channel transistor;

wherein the common node of the gate and drain serves as an output terminal.

12. The operational amplifier according to claim 1, wherein the second level shifting stage comprises:

an n-channel transistor having a source connected to the second power supply voltage and a gate connected to a second bias voltage; and

a p-channel transistor having a source connected to the output terminal of the second amplifying stage, a gate and a drain commonly connected to each other to form a common node connected to a drain of the n-channel transistor;

wherein the common node of the gate and drain serves as an output terminal.

13. The operational amplifier according to claim 8, wherein

the first phase compensation circuit comprises an MOS resistor composed of a p-channel transistor and an n-channel transistor, and a capacitor respectively provided between the second level shifting stage and the output terminal of the outputting stage and serially connected to one another in this order;

and wherein the gate of the p-channel transistor is connected to the second power supply voltage and the gate of the n-channel transistor is connected to the first power supply voltage.

14. The operational amplifier according to claim 8, wherein

the second phase compensation circuit comprises an MOS resistor composed of a p-channel transistor and an n-channel transistor, and a capacitor respectively provided between the first level shifting stage and the output terminal of the outputting stage and serially connected to one another in this order;

and wherein the gate of the p-channel transistor is connected to the second power supply voltage and the gate of the n-channel transistor is connected to the first power supply voltage.

15. An operational amplifier comprising first and second differential amplifying means for differentially amplifying input signals, first and second amplifying means for amplifying outputs of the first and second differential amplifying means, first and second level shifting means for level shifting outputs of the first and second amplifying means, and outputting means having a p-channel MOS transistor a source of which is connected to a first power supply voltage, and an n-channel MOS transistor a source of which is connected to a second power supply voltage, said outputting means executing complementary operation in response to outputs of the first and second level shifting means, wherein the operational amplifier further comprises:

first and second overcurrent detecting circuits for detecting outputs of the first and second level shifting means; and

first and second current compensation means for compensating increments of current of the first and second amplifying means in response to detected outputs of the first and second overcurrent detecting circuits.

16. The operational amplifier according to claim 15, wherein the first overcurrent detecting circuit includes means for detecting the change in voltage of the first and second level shifting means in opposite phase, and overlaying the amount of change in voltage onto a threshold voltage of the n-channel MOS transistor while the second power supply voltage serves as a reference voltage as the detected output.

17. The operational amplifier according to claim 15, wherein the second overcurrent detecting circuit includes means for detecting the change in voltage of the first and second level shifting means in opposite phase, and overlaying the amount of change in voltage onto a threshold voltage of the p-channel MOS transistor while the first power supply voltage serves as a reference voltage as the detected output.

18. The operational amplifier according to claim 17, wherein the p-channel MOS transistor and the n-channel MOS transistor for detecting the first and second overcurrent have the ratio of channel width with respect to channel length which is sufficiently smaller than that of transistors of the outputting means having a p-channel MOS transistor a source of which is connected to the first power supply voltage and an n-channel MOS transistor a source of which is connected to the second power supply voltage for executing complementary operation in response to outputs of the first and second level shifting means.

19. The operational amplifier according to claims 18, wherein the first current compensation means comprises an n-channel MOS transistor which is disposed in parallel with the n-channel MOS transistor of the first amplifying means.

20. The operational amplifier according to claims 19, wherein the second current compensation means comprises a p-channel MOS transistor which is disposed in parallel with the p-channel MOS transistor of the second amplifying means.