Phase adjustment circuit including a ring oscillator in a phase locked loop

• US 6,005,445 A
• Filed: 12/10/1997
• Issued: 12/21/1999
• Est. Priority Date: 12/29/1996
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Katakura, Masayuki
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US08/988,010
• Time in Patent Office: 741 Days
• Field of Search: 331/34, 331/57, 331/74, 331/45, 331/177 R
• US Class Current: 331/34
• CPC Class Codes: H03B 27/00 Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs
• CPC Class Codes: H03K 2005/00026 controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0998 using phase interpolation

Abstract

A phase adjustment circuit includes a ring oscillator which is phase locked to an external pixel clock by a phase locked loop. The ring oscillator is formed of n number of stages of variable delay circuits providing n+1 outputs of substantially equal phase differences. A control signal generation circuit is responsive to a phase control signal to generate n+1 weighting coefficients for weighting the n+1 outputs from the ring oscillator in a weighting circuit which produces a phase adjusted output signal.

Claims

1. A phase adjustment circuit, comprising:

a voltage controlled oscillation circuit provided with serially connected n number of stages (n is a positive integer) of variable delay circuits and performing negative feedback of the output of the final stage variable delay circuit to the input of the initial stage variable delay circuit;

a phase locked loop means for comparing phases of the output of the voltage controlled oscillation circuit and a clock supplied from an external unit, outputting a delay control signal to control the delay time in each stage of variable delay circuit of the voltage controlled oscillation circuit, and locking the phase;

a control signal generation circuit which outputs k (k is an integer of at least

     3) number of weighting coefficient signals based on a phase control signal supplied from an external unit and interpolates the middle section so that the maximum number of weighting coefficient signals are given at substantially equal intervals with respect to the phase control signal and so that the sum of the weighting coefficients is substantially constant; and

a weighting means for weighting each of k number of signals of substantially equal phase differences taken out from the stages of the variable delay circuits in the voltage controlled oscillation circuit with a respective one of the k number of weighting coefficient signals output by the control signal generation circuit and outputting the result as the output signal of the phase adjustment circuit.

2. A phase adjustment circuit as set forth in claim 1, wherein

the control signal generation circuit is constituted provided with k-1 number of sets of a pair of common-emitter differential transistors comprised of a first and second transistor with emitters connected and of a current source connected to the common emitters of the pair of the common-emitter differential transistors;

a first weighting coefficient signal output is taken out from a collector of the first transistor of the first pair of common-emitter differential transistors, a k-th weighting coefficient signal output is taken out of, a collector of the second transistor of a k-1-th pair of common-emitter differential transistors, a collector of the second transistor of an i-th (i is at least 1 and not more than k-2) pair of common-emitter differential transistors is connected to a collector of the first transistor of an i+1-th pair of common-emitter differential transistors, and an i+1-th weighting coefficient signal output is taken out of a collector of the first transistor of the i-th pair of common-emitter differential transistors, and

a phase control signal is supplied to the base of one transistor of each of the first and second transistors of the k-1 number of pairs of common-emitter differential transistors, and a voltage obtained by substantially equally dividing first and second reference potentials by k-1 is supplied to the base of the other transistor.

3. A phase adjustment circuit as set forth in claim 1, wherein the variable delay circuit is constituted with

a current mode logic (CML) buffer circuit provided with two emitter-follower circuits having transistors and current sources connected to the emitters of the transistors and controlled by the delay control signal from the phase locked loop means and with a pair of common-emitter differential transistors comprising a second and third transistor with connected emitters and

a capacitance element connected between emitters of the transistors of the two emitter-follower circuits.

4. A phase adjustment circuit as set forth in claim 1, wherein the number k of the weighting coefficient signals or the substantially equal phase difference signals taken out of the voltage controlled oscillation circuit is equal to n+1, the phases of the first to n-th substantially equal phase difference signals are arranged so as to equally divide 180°

by n; and

an n+1-th substantially equal phase difference signal has an inverse phase to that of the first substantially equal phase difference signal.

5. A phase adjustment circuit as set forth in claim 1, wherein the number k of the weighting coefficient signals or the substantially equal phase difference signals taken out of the voltage controlled oscillation circuit is equal to 2·

n+1;

phases of the first to 2·

n-th substantially equal phase difference signals are arranged so as to equally divide 360°

by n; and

a 2·

n+1-th substantially equal phase difference signal has the same phase as that of the first substantially equal phase difference signal.