Receiver with sigma-delta analog-to-digital converter for sampling a received signal

• US 6,005,506 A
• Filed: 12/09/1997
• Issued: 12/21/1999
• Est. Priority Date: 12/09/1997
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Butterfield, Daniel K., Bazarjani, Seyfollah S., Ciccarelli, Steven C., Younis, Saed G.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): WAMSLEY, PATRICK G
• Application Number:
  US08/987,306
• Time in Patent Office: 742 Days
• Field of Search: 341/143, 341/155, 375/279, 375/280, 375/261, 375/329, 375/332, 375/340, 375/316, 375/322, 329/356
• US Class Current: 341/143
• CPC Class Codes: H03D 3/007 by converting the oscillations into two quadrature related signals H03D3/245 takes precedence
• CPC Class Codes: H03D 7/165 at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/0032 with analogue quadrature frequency conversion to and from the baseband quadrature modulators and demodulators per se H03D3/007, H03C3/40
• CPC Class Codes: H04B 1/0039 using DSP [Digital Signal Processor] quadrature modulation and demodulation
• CPC Class Codes: H04B 1/26 for superheterodyne receivers multiple frequency-changing H03D7/16

Abstract

A receiver comprising a sigma-delta analog-to-digital converter (ΣΔ ADC) can be utilized in one of four configurations, as a subsampling bandpass receiver, a subsampling baseband receiver, a Nyquist sampling bandpass receiver, or a Nyquist sampling baseband receiver. For subsampling ΣΔ receivers, the sampling frequency is less than twice the center frequency of the input signal into the ΣΔ ADC. For Nyquist sampling ΣΔ receivers, the sampling frequency is at least twice the highest frequency of the input signal into the ΣΔ ADC. For baseband ΣΔ receivers, the center frequency of the output signal from the ΣΔ ADC is approximately zero or DC. For bandpass ΣΔ receivers, the center frequency of the output signal from the ΣΔ ADC is greater than zero. The sampling frequency can be selected based on the bandwidth of the input signal to simplify the design of the digital circuits used to process the output samples from the ΣΔ ADC. Furthermore, the center frequency of the input signal can be selected based on the sampling frequency and the bandwidth of the input signal. The ΣΔ ADC within the receiver provides many benefits.

Claims

1. A receiver for demodulating an RF signal comprising:

a front end stage configured to receive and downconvert said RF signal to an intermediate (IF) signal, said IF signal having a center frequency and a two-sided bandwidth;

a sigma-delta analog-to-digital converter coupled to said front end stage, said Σ

Δ

ADC configured to receive and sample said IF signal to provide IF samples, said Σ

Δ

ADC being clocked at a sampling frequency; and

a digital signal processor coupled to said Σ

Δ

ADC, said digital signal processor configured to receive and demodulate said IF samples in accordance with a modulation format used to produce said RF signal.

2. The receiver of claim 1 wherein said digital signal processor comprises:

a digital filter configured to receive and filter said IF samples to provide filtered samples, said digital filter further configured to decimate said filtered samples by a decimation ratio.

3. The receiver of claim 2 wherein said digital signal processor further comprises:

a demodulator coupled to said digital filter, said demodulator configured to receive and downconvert said filtered samples to provide inphase samples and quadrature samples.

4. The receiver of claims 3 wherein said digital signal processor further comprises:

two digital lowpass filters coupled to said demodulator, one lowpass filter configured to receive and filter said inphase samples and the other lowpass filter configured to receive and filter said quadrature samples.

5. The receiver of claim 4 wherein said lowpass filters perform matched filtering of said inphase and quadrature samples.

6. The receiver of claim 2 wherein a frequency response of said digital filter can be adjusted based on an operating mode of said receiver.

7. The receiver of claim 6 wherein said sampling frequency is selected based on said decimation ratio of said digital filter and said two-sided bandwidth of said IF signal.

8. The receiver of claim 1 wherein said Σ

Δ

ADC is a subsampling bandpass Σ

Δ

ADC.

9. The receiver of claim 8 wherein said center frequency of said IF signal is approximately 0.25·

(2n+1) times said sampling frequency where n is an integer greater than one.

10. The receiver of claim 9 wherein n is equal to two.

11. The receiver of claim 8 wherein said center frequency of said IF signal is 0.25·

(2n) times said sampling frequency, where n is an integer greater than one.

12. The receiver of claim 11 wherein n is equal to two.

13. The receiver of claim 1 wherein said IF signal comprises a CDMA signal.

14. The receiver of claim 13 wherein said center frequency of said IF signal is approximately 116.5 MHz.

15. The receiver of claim 14 wherein said sampling frequency is approximately 66.6 MHz.

16. The receiver of claim 13 wherein said two-sided bandwidth is approximately 1.23 MHz.

17. The receiver of claim 1 wherein said Σ

Δ

ADC comprises multiple loops, wherein each loop can be selectively turned ON or OFF depending on a specified requirement.

18. The receiver of claim 17 wherein said specified requirement is a required dynamic range.

19. The receiver of claim 1 wherein said Σ

Δ

ADC is a MASH Σ

Δ

ADC.

20. The receiver of claim 19 wherein said MASH Σ

Δ

ADC is a MASH 4-4 Σ

Δ

ADC.

21. The receiver of claim 1 wherein said Σ

Δ

ADC is a multi-sampling Σ

Δ

ADC.

22. The receiver of claim 21 wherein said Σ

Δ

ADC is a double-sampling Σ

Δ

ADC.

23. The receiver of claim 1 wherein said Σ

Δ

ADC is a subsampling baseband Σ

Δ

ADC.

24. The receiver of claim 1 wherein said Σ

Δ

ADC is a Nyquist sampling bandpass Σ

Δ

ADC.

25. The receiver of claim 1 wherein said Σ

Δ

ADC is a Nyquist sampling baseband Σ

Δ

ADC.

26. The receiver of claim 1 wherein said sampling frequency is selected based on said two-sided bandwidth of said IF signal.

27. The receiver of claim 1 wherein said Σ

Δ

ADC provides four or more bits of resolution.

28. The receiver of claim 1 wherein said Σ

Δ

ADC is clocked at an oversampling ratio of sixteen or greater.

29. The receiver of claim 1 wherein said Σ

Δ

ADC is a single-loop Σ

Δ

ADC.

30. The receiver of claim 1 wherein modulation format is quadrature phase shift keying (QPSK).

31. The receiver of claim 1 wherein modulation format is offset quadrature phase shift keying (OQPSK).

32. The receiver of claim 1 wherein modulation format is m-ary phase shift keying (m-PSK).

33. A receiver for demodulating an RF signal comprising:

a front end stage configured to receive and downconvert said RF signal to an intermediate (IF) signal;

a quadrature demodulator coupled to said front end stage, said quadrature demodulator configured to receive and downconvert said IF signal into baseband I and Q signals; and

two Σ

Δ

ADCs coupled to said quadrature demodulator, one Σ

Δ

ADC configured to receive said baseband I signal and one Σ

Δ

ADC configured to receive said baseband Q signal, said Σ

Δ

ADCs independently sampling said baseband I and Q signals to produce baseband samples, said Σ

Δ

ADC being clocked at a sampling frequency.

34. The receiver of claim 33 wherein said Σ

Δ

ADCs are MASH Σ

Δ

ADC.

35. The receiver of claim 34 wherein said Σ

Δ

ADCs are MASH 4-4 Σ

Δ

ADC.

36. The receiver of claim 33 wherein said Σ

Δ

ADCs are Nyquist sampling baseband Σ

Δ

ADCs.

37. The receiver of claim 33 further comprising:

two filters coupled between said quadrature demodulator and said Σ

Δ

ADCs, each filter configured to receive and filter a respective baseband signal to provide a filtered signal, wherein each Σ

Δ

ADC independently samples a respective filtered signal to provide baseband samples.

38. The receiver of claim 33 wherein said Σ

Δ

ADCs are a multi-sampling Σ

Δ

ADCs.