Single ended simpler dual port memory cell
First Claim
1. A single ended simplex dual port memory cell comprising:
- a read transistor for reading data to the memory cell, having a first gate width-to-length ratio;
a write transistor for writing data to the memory cell, having a second gate width-to-length ratio;
a first pass gate transistor having a third gate width-to-length ratio, receiving a first input and being coupled to the read transistor and to a first port; and
a second pass gate transistor having fourth gate width-to-length ratio, receiving a second input independent of the first input, and coupled to the write transistor and to a second port independent of the first port,wherein (a) the ratio of (i) the first gate width-to-length ratio to (ii) the third gate width-to-length ratio is greater than 1.5, and (b) the ratio of (iii) the second gate width-to-length ratio to the (iv) fourth gate width-to-length ratio is less than 1.5.
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Abstract
A single ended simplex dual port memory cell is described. One port of the memory cell is dedicated for writing operations and the other port of the memory cell is dedicated for reading operations. A bit of data received from the first port can be stored in the memory cell. The second port can detect the memory cell contents substantially simultaneously as the memory cell is storing a bit of data from the first port. Each port is optimized for its respective dedicated operation. In other words, one port is optimized for write operations and the other port is optimized for read operations. Because one port of the memory cell is optimized for write operations and the other port of the memory cell is optimized for read operations, the cell does not require multiple wordline voltages for each port.
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Citations
21 Claims
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1. A single ended simplex dual port memory cell comprising:
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a read transistor for reading data to the memory cell, having a first gate width-to-length ratio; a write transistor for writing data to the memory cell, having a second gate width-to-length ratio; a first pass gate transistor having a third gate width-to-length ratio, receiving a first input and being coupled to the read transistor and to a first port; and a second pass gate transistor having fourth gate width-to-length ratio, receiving a second input independent of the first input, and coupled to the write transistor and to a second port independent of the first port, wherein (a) the ratio of (i) the first gate width-to-length ratio to (ii) the third gate width-to-length ratio is greater than 1.5, and (b) the ratio of (iii) the second gate width-to-length ratio to the (iv) fourth gate width-to-length ratio is less than 1.5. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A memory cell, comprising:
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a first port having an associated first passgate, read transistor, first wordline and first bitline; and a second port having an associated second passgate, write transistor, second wordline and a second bitline, wherein a first resistivity ratio of said first passgate to said read transistor is greater than a second resistivity ratio of said second passgate to said write transistor and said first and second wordlines are independent of one another.
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Specification