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Single ended simpler dual port memory cell

  • US 6,005,796 A
  • Filed: 01/30/1997
  • Issued: 12/21/1999
  • Est. Priority Date: 12/22/1994
  • Status: Expired due to Term
First Claim
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1. A single ended simplex dual port memory cell comprising:

  • a read transistor for reading data to the memory cell, having a first gate width-to-length ratio;

    a write transistor for writing data to the memory cell, having a second gate width-to-length ratio;

    a first pass gate transistor having a third gate width-to-length ratio, receiving a first input and being coupled to the read transistor and to a first port; and

    a second pass gate transistor having fourth gate width-to-length ratio, receiving a second input independent of the first input, and coupled to the write transistor and to a second port independent of the first port,wherein (a) the ratio of (i) the first gate width-to-length ratio to (ii) the third gate width-to-length ratio is greater than 1.5, and (b) the ratio of (iii) the second gate width-to-length ratio to the (iv) fourth gate width-to-length ratio is less than 1.5.

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