Methods and circuits for single-memory dynamic cell multivalue data storage

• US 6,005,799 A
• Filed: 08/06/1998
• Issued: 12/21/1999
• Est. Priority Date: 08/06/1998
• Status: Expired due to Term

• Current Assignee: Foothills IP LLC
• Original Assignee: Silicon Aquarius
• Inventors: Rao, G. R. Mohan
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US09/130,136
• Time in Patent Office: 502 Days
• Field of Search: 365/168, 365/149, 365/205, 365/207
• US Class Current: 365/168
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits

Abstract

A multivalue dynamic random access memory cell and method therefor are provided. Sense circuitry for sensing a most significant bit (MSB) and a least significant bit (LSB) of a binary data value are coupled to an unsegmented complementary bitline pair. The binary data is represented by a multilevel voltage stored on a storage element in the DRAM cell. A reference signal is provided to the sense circuitry, wherein the reference signal is independent of a precharge on the bitline pair. Cross-coupling elements offset the reference signal in response to the sensing of the MSB, whereby the voltage levels corresponding to the LSB are sensed. Following a read, the multilevel data value is restored on the storage element by a restore/write unit including a programmable voltage supply. The detected MSB/LSB pair are input to the restore/write unit which outputs the corresponding voltage level to the DRAM cell. A write is effected using the same restore/write unit with the binary datum to be stored input to the restore/write unit.

Claims

1. A multivalue dynamic random access memory (DRAM) cell comprising:

first circuitry operable for sensing a least significant bit (LSB) of a stored data value, said first circuitry having first and second nodes operable for coupling to a respective one of a complementary bitline pair;

a first storage element operable for storing a reference voltage coupled to said first node wherein said reference voltage is independent of a precharge voltage on said bitline pair;

a second storage element operable for storing said reference voltage coupled to said second node;

second circuitry operable for sensing a most significant bit (MSB) and having third and fourth nodes for coupling to a respective one of said complementary bitline pair;

a first cross-coupling element coupled to said first storage element and said fourth node to form a dynamic voltage divider with said first storage element, said first cross-coupling element operable for providing a signal for offsetting said reference signal in response to said MSB; and

a second cross-coupling element coupled to said second storage element and said third node to form a dynamic voltage divider with said second storage element, said second cross-coupling element operable for providing a signal for offsetting said reference signal in response to said MSB.

2. The memory cell of claim 1 wherein said first and second storage elements each comprise a gate-substrate capacitance of a conductor oxide semiconductor device.

3. The memory cell of claim 1 wherein said first and second storage elements comprise a conventional capacitor.

4. The memory cell of claim 1 further comprising a third storage element operable for coupling to a first one of a complementary bitline pair, said third storage element being operable for storing said stored data value.

5. The memory cell of claim 1 wherein said first and second cross-coupling elements comprise first and second cross-coupling capacitors.

6. The memory cell of claim 1 further comprising a first switch for coupling said first node to a first one of said pair of complementary bitlines and a second switch for coupling said second node to a second one of said pair of complementary bitlines.

7. The memory cell of claim 6 wherein said first and second switches comprise metal oxide semiconductor devices (FETs).

8. The memory cell of claim 1 further comprising a first switch for coupling said third node to a first one of said pair of complementary bitlines and a second switch for coupling said fourth node to a second one of said pair of complementary bitlines.

9. The memory cell of claim 8 wherein said first and second switches comprise metal oxide semiconductor devices (FETs).

10. A random access memory comprising:

an array of rows and columns of memory cells;

plurality of bitlines, each associated with a one of said plurality of columns,

wherein each of said memory cells comprises;

first circuitry operable for sensing a most significant bit (MSB) of a stored data value, said first circuitry coupled to a corresponding one of said plurality of bitlines;

second circuitry operable for sensing a least significant bit (LSB) of a stored data value, said first circuitry coupled to said corresponding one of said plurality of bitlines, wherein said MSB and said LSB are output on said corresponding bitline;

a data storage element operable for coupling to said corresponding bitline; and

a write/restore unit coupled to said plurality of bitlines, said write/restore unit including a programmable voltage supply operable for receiving a multibit binary data value and, in response thereto, outputting a multilevel stored data value for storage in said data storage element.

11. The memory of claim 10 wherein said second circuitry includes first and second storage elements operable for storing a reference voltage respectively coupled to first and second nodes of a first sense amplifier, said reference voltage being operable for providing a reference signal level to said sense amplifier, and wherein said reference signal level is independent of a precharge on said plurality of bitlines.

12. The memory of claim 11 wherein said first circuitry includes a second sense amplifier having third and fourth nodes, and first and second cross-coupling elements respectively coupled between said first storage element and said fourth node and between said second storage element and said third node, wherein said cross-coupling elements are operable for shifting said reference signal level in response to said MSB.

13. The memory of claim 11 wherein said first and second each comprise a gate-substrate capacitance of a metal oxide semiconductor device.

14. A method of storing a plurality of data bits in a random access memory cell comprising:

for a write to said memory cell;

providing said plurality of data bits to a programmable voltage supply, said programmable voltage supply outputting a preselected voltage representing said plurality of data bits;

storing said preselected voltage in a storage element in said cell;

for a read operation;

sensing a most significant bit (MSB) of said data bits in response to said preselected voltage in said storage element;

sensing a least significant bit (LSB) of said data bits in response to said preselected voltage in said storage element and said MSB;

following a read operation, restoring said preselected voltage in said storage element, said step of restoring comprising;

providing said MSB and said LSB to said programmable voltage source; and

outputting said preselected voltage in response to said MSB and said LSB.

15. The method of claim 14 wherein said step of sensing said MSB comprises the steps of providing sense circuitry for sensing said MSB;

providing a preselected reference signal to said first sense circuitry, wherein said preselected reference voltage is independent of a precharge on said first sense circuitry; and

differentially comparing said preselected voltage and said reference signal.

16. The method of claim 14 wherein said step of sensing said LSB comprises the steps of:

providing sense circuitry for sensing said LSB, said circuitry having a pair of differential inputs;

providing a preselected reference signal to said pair of differential inputs, wherein said preselected reference voltage is independent of a precharge on said first sense circuitry;

differentially shifting said reference signal by a predetermined shift in response to said MSB;

providing said preselected voltage to one of said pair of differential inputs; and

activating said sense circuitry, wherein said sense circuitry assumes a one of two equilibrium states in response to signals provided on said differential inputs.