Nonvolatile semiconductor memory device using a bit line potential raised by use of a coupling capacitor between bit lines

• US 6,005,802 A
• Filed: 10/07/1998
• Issued: 12/21/1999
• Est. Priority Date: 10/09/1997
• Status: Expired due to Term

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takeuchi, Ken, Tanaka, Tomoharu, Nakamura, Hiroshi
• Primary Examiner(s): TRAN, ANDREW Q
• Application Number:
  US09/167,551
• Time in Patent Office: 440 Days
• Field of Search: 365/185.02, 365/185.17, 365/185.21, 365/185.25
• US Class Current: 365/185.02
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A nonvolatile semiconductor memory device includes a memory cell section including at least one nonvolatile memory cell, a first bit line connected to one end of the memory cell section, and a second bit line capacitively coupled with the first bit line. At the data programming time, the first bit line is set to a first voltage, thereafter rendered electrically floating, the voltage of the second bit line is changed to a second voltage after the first bit line is rendered electrically floating, and then the first bit line which is set in the electrically floating state is capacitively coupled with second bit line to change the voltage of the first bit line to a third voltage higher than the first and second voltages.

Claims

1. A nonvolatile semiconductor memory device comprising:

a memory cell section including at least one nonvolatile memory cell;

a first signal line connected to one end of said memory cell section; and

a second signal line capacitively coupled with said first signal line;

wherein said first signal line is set to a first voltage, thereafter rendered electrically floating, and then the voltage of said first signal line is changed to a third voltage different from the first voltage by changing the voltage of said second signal line to a second voltage after said first signal line is rendered electrically floating.

2. A nonvolatile semiconductor memory device according to claim 1, wherein said first signal line and said second signal line are connected to each other to change the voltage of said first and second signal lines to a fourth voltage after the voltage of said first signal line is changed to the third voltage.

3. A nonvolatile semiconductor memory device according to claim 2, wherein said first signal line or said second signal line is changed to a fifth voltage after the voltages of said first and second signal lines are changed to the fourth voltage.

4. A nonvolatile semiconductor memory device according to claim 2, wherein the fourth voltage is higher than a power supply voltage.

5. A nonvolatile semiconductor memory device according to claim 2, wherein the first and second voltages are power supply voltages.

6. A nonvolatile semiconductor memory device according to claim 1, wherein said first signal line is changed to a fifth voltage after the voltage of said first signal line is changed to the third voltage.

7. A nonvolatile semiconductor memory device according to claim 1, wherein the first and second voltages are power supply voltages.

8. A nonvolatile semiconductor memory device according to claim 1, wherein the first voltage is 0 V.

9. A nonvolatile semiconductor memory device according to claim 1, wherein said first and second signal lines are bit lines.

10. A nonvolatile semiconductor memory device comprising:

a memory cell section including at least one nonvolatile memory cell;

a first signal line connected to one end of said memory cell section; and

a second signal line capacitively coupled with said first signal line;

wherein said first signal line is set to a first voltage, thereafter rendered electrically floating, and then the voltage of said first signal line is changed from the first voltage to an unselected programming voltage by changing the voltage of said second signal line to a second voltage after said first signal line is rendered electrically floating.

11. A nonvolatile semiconductor memory device according to claim 10, which further comprises a data latch circuit for storing programming data into said memory cell section and wherein the voltage of one of said first and second signal lines set at the unselected programming voltage is changed to a preset programming voltage according to programming data stored in said data latch circuit.

12. A nonvolatile semiconductor memory device according to claim 11, wherein the unselected programming voltage is transferred to said memory cell section before the voltage of one of said first and second signal lines is changed to the preset programming voltage.

13. A nonvolatile semiconductor memory device according to claim 10, wherein the unselected programming voltage is higher than a power supply voltage.

14. A nonvolatile semiconductor memory device according to claim 10, wherein the first and second voltages are power supply voltages.

15. A nonvolatile semiconductor memory device according to claim 10, wherein said first and second signal lines are bit lines.

16. A nonvolatile semiconductor memory device comprising:

a memory cell section including at least one nonvolatile memory cell;

a first signal line connected to one end of said memory cell section; and

a second signal line capacitively coupled with said first signal line;

wherein said first signal line is set to a first voltage, thereafter rendered electrically floating, and the voltage of said first signal line is changed to a third voltage different from the first voltage by changing the voltage of said second signal line to a second voltage after said first signal line is rendered electrically floating, and then said first signal line and said second signal line are connected to each other to set the voltages of said first and second signal lines to an unselected programming voltage after the voltage of said first signal line is set to the third voltage.

17. A nonvolatile semiconductor memory device according to claim 16, which further comprises a data latch circuit for storing data to be programmed into said memory cell section and wherein the voltage of one of said first and second signal lines set at the unselected programming voltage is changed to a preset programming voltage according to programming data stored in said data latch circuit.

18. A nonvolatile semiconductor memory device according to claim 17, wherein the unselected programming voltage is transferred to said memory cell section before the voltage of one of said first and second signal lines is changed to the preset programming voltage.

19. A nonvolatile semiconductor memory device according to claim 16, wherein the unselected programming voltage is higher than a power supply voltage.

20. A nonvolatile semiconductor memory device according to claim 16, wherein the first and second voltages are power supply voltages.

21. A nonvolatile semiconductor memory device according to claim 16, wherein said first and second signal lines are bit lines.

22. A nonvolatile semiconductor memory device comprising:

a memory cell section including at least one nonvolatile memory cell;

a first signal line connected to one end of said memory cell section;

a second signal line capacitively coupled with said first signal line; and

a data latch circuit for storing data to be programmed into said memory cell section;

wherein said first signal line is set to a first voltage, thereafter rendered electrically floating, then the voltage of said first signal line is changed to a third voltage different from the first voltage by changing the voltage of said second signal line to a second voltage after said first signal line is rendered electrically floating, and the voltage of said first signal line is changed to a preset programming voltage according to programming data stored in said data latch circuit after the voltage of said first signal line is changed to the third voltage.

23. A nonvolatile semiconductor memory device according to claim 22, which further comprises a bias circuit for biasing said second signal line and wherein the second voltage is supplied from said bias circuit.

24. A nonvolatile semiconductor memory device according to claim 23, wherein the second voltage supplied from said bias circuit to said second signal line is an external power supply voltage and the preset programming voltage supplied from said data latch circuit to said first signal line contains an internal power supply voltage.

25. A nonvolatile semiconductor memory device according to claim 24, which further comprises a voltage lowering circuit wherein said voltage lowering circuit supplies the internal power supply voltage which is lower than the external power supply voltage.

26. A nonvolatile semiconductor memory device according to claim 25, wherein the external power supply voltage is supplied to said bias circuit via a first power supply terminal and the external power supply voltage is supplied to said voltage lowering circuit via a second power supply terminal different from said first power supply terminal.

27. A nonvolatile semiconductor memory device according to claim 22, wherein the first voltage is 0 V.

28. A nonvolatile semiconductor memory device according to claim 22, wherein said first and second signal lines are bit lines.