Nonvolatile configuration cells and cell arrays

• US 6,005,806 A
• Filed: 09/16/1996
• Issued: 12/21/1999
• Est. Priority Date: 03/14/1996
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Madurawe, Raminda U., Sansbury, James D.
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US08/710,398
• Time in Patent Office: 1,191 Days
• Field of Search: 365/185.23, 365/185.05, 365/185.29, 365/148, 365/154, 326/39
• US Class Current: 365/185.23
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17772 for powering on or off
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17784 for supply voltage

Abstract

A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).

Claims

1. An integrated circuit comprising:

a first plurality of conductors extending in a first direction for conducting logic signals;

a second plurality of conductors in a second direction, transverse to said first direction, for conducting logic signals; and

a plurality of programmable intersections for programmably coupling said first plurality of conductors to said second plurality of conductors, wherein a programmable intersection comprises;

an output node for providing approximately full-rail output voltages;

a pull-down resistor, coupled between a first voltage source at a first voltage level and said output node; and

a nonvolatile memory element, coupled between said output node and a second voltage source at a second voltage level, wherein said second voltage level is above said first voltage level, said nonvolatile memory element stores data and retains said data, even when power is removed from said programmable logic device.

3. The integrated circuit of claim 1 wherein said pull-down resistor has a resistance of more than about ten megaohms.

4. The integrated circuit of claim 1 wherein said pull-down resistor has a resistance from about one hundred megaohms to about ten gigaohms.

5. The integrated circuit of claim 1 wherein said pull-down resistor has a resistance of about one gigaohm.

6. The integrated circuit of claim 1 wherein one of said plurality of programmable intersections consumes less than about two microamps.

7. The integrated circuit of claim 1 wherein said programmable intersection consumes no static power when said nonvolatile memory element is programmed, said programmable intersection programmably decoupling said a first conductor from a second conductor.

8. The integrated circuit of claim 1 further comprising:

a plurality of logic array blocks, programmably coupled to said first plurality of conductors and said second plurality of conductors.

2. An integrated circuit comprising:

a first plurality of conductors extending in a first direction for conducting logic signals;

a second plurality of conductors in a second direction, transverse to said first direction, for conducting logic signals; and

a plurality of programmable intersections for programmably coupling said first plurality of conductors to said second plurality of conductors, wherein a programmable intersection comprises;

an output node for providing approximately full-rail output voltages;

a pull-down resistor, coupled between a first voltage source at a first voltage level and said output node;

a nonvolatile memory element, coupled between said output node and a second voltage source at a second voltage level, wherein said second voltage level is above said first voltage level, said nonvolatile memory element stores data and retains said data, even when power is removed from said programmable logic device; and

a pass transistor, programmably coupled between a first conductor and a second conductor, wherein a gate of said pass transistor is coupled to said output node, and said output node is at about said first voltage level for programmably decoupling said first conductor from said second conductor, and at about said second voltage level when for programmably coupling said first conductor to said second conductor.

9. An integrated circuit comprising:

a plurality of configurable logic elements, wherein said configurable logic elements are configured by configuring a plurality of programmable elements, a programmable element comprising;

a pull-down resistor, coupled between a first voltage source at a first voltage level and an output node;

a nonvolatile memory element, coupled between said output node and a second voltage source at a second voltage level, wherein said second voltage level is above said first voltage level, said nonvolatile memory element stores data and retains said data, even when power is removed from said programmable logic device; and

an output node coupled to said pull-down resistor and said nonvoltatile memory element, said output node providing a first output level representative of a first logical state and a second output level representative of a second logical state.

10. A nonvolatile memory cell for an integrated circuit comprising:

an output node, for providing approximately full-rail output voltages;

a pull-down device, coupled between a first voltage source at a first voltage level and said output node; and

a nonvolatile programmable memory element, coupled between said output node and a second voltage source at a second voltage level,

wherein said second voltage level is above said first voltage level, said nonvolatile programmable memory element stores data and retains said data, even when power is removed from said integrated circuit,

wherein said pull-down device provides a first pull-down current when said nonvolatile memory cell stores a logic low and a second pull-down current when said nonvolatile memory cell stores a logic high, said first pull-down current pulls said output node to about said first voltage level when said nonvolatile programmable memory element is programmed, said second pull-down current is drained through said nonvolatile programmable memory element from said second voltage source so that said output node is about said second voltage level when said nonvolatile programmable memory element is erased.

11. The nonvolatile memory cell of claim 10 wherein said pull-down device is a polysilicon resistor.

12. The nonvolatile memory cell of claim 10 wherein said pull-down device is a thin-film transistor.

13. The nonvolatile memory cell of claim 10 wherein said pull-down device is resistor having a resistance from about one hundred megaohms to about ten gigaohms.

14. The nonvolatile memory cell of claim 10 wherein said pull-down device is resistor having a resistance of about one gigaohm.

15. The nonvolatile memory cell of claim 10 wherein when said second pull-down current is less than about five microamps.

16. The nonvolatile memory cell of claim 10 wherein when said second pull-down current is less than about two microamps.

17. The nonvolatile memory cell of claim 10 wherein said nonvolatile memory consumes no static power when said nonvolatile programmable memory element is programmed.

18. The nonvolatile memory cell of claim 10 wherein said nonvolatile programmable memory element is a floating gate device.

19. The nonvolatile memory cell of claim 10 further comprising:

a floating gate, coupled to said nonvolatile programmable memory cell; and

a tunnel dielectric, for providing charge to and removing charge from said floating gate.

20. The nonvolatile memory cell of claim 19 further comprising:

a tunnel diode, positioned beneath said tunnel dielectric, wherein said tunnel diode is a source of electrons; and

a select transistor, wherein high voltages are supplied through said select transistor to said tunnel diode to provide charge to and remove charge from said floating gate through said tunnel dielectric.

21. The nonvolatile memory cell of claim 19 wherein said nonvolatile programmable memory element comprises a program transistor and a read transistor, sharing a common floating gate.

22. The nonvolatile memory cell of claim 10 wherein said pull-down device has a first impedance when said programmable memory element is programmed and a second impedance when said programmable memory element is erased.

23. The nonvolatile memory cell of claim 10 wherein when said nonvolatile programmable memory element is programmed using quantum-mechanical tunneling.

24. The nonvolatile memory cell of claim 10 wherein when said nonvolatile programmable memory element is programmed using hot electrons.