Test mode entrance through clocked addresses

• US 6,005,814 A
• Filed: 04/03/1998
• Issued: 12/21/1999
• Est. Priority Date: 04/03/1998
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Mulholland, Sean B., Allan, James D.
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US09/054,654
• Time in Patent Office: 627 Days
• Field of Search: 365/200, 365/201, 365/233, 371/21.1, 371/21.2, 371/21.3
• US Class Current: 365/201
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G11C 29/46 Test trigger logic
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits

Abstract

A robust system for entering a test mode in an integrated circuit, for example, a memory device, greatly eliminates the probability of unintentionally entering the test mode, yet provides a system of access through a precise address and control pin sequence. By using an existing control pin present on the integrated circuit as a clock signal input for a series of latches, the present scheme sets up a number of address with predetermined values in order to create a key that is correct only if all the addresses are at the correct values. The key, combined with the clock signal input, allows a test mode enable signal to pass through each latch in a series. By further requiring that the address sequence for the key be input during an otherwise "illegal" operation for the integrated circuit, the present scheme further ensures that unintentional entry to the test mode is avoided.

Claims

1. A method, comprising generating a test mode enable signal in an integrated circuit device by propagating a logic signal through a series of key stages in response to a number of keys of a key sequence and a clock signal.

2. A method of claim 1 wherein said integrated circuit device is a memory device and said keys of said key sequence comprise a unique series of addresses.

3. The method of claim 2 wherein said clock signal is applied to a control signal pin of the memory device.

4. The method of claim 1 wherein said key stages each comprise a D-type flip-flop.

5. The method of claim 4 wherein each of said key stages is responsive to a different corresponding one of said unique keys.

6. The method of claim 5 wherein each of said keys is a unique address.

7. The method of claim 6 wherein said logic signal is latched by a first of said key stages only when a corresponding first one of said unique addresses selects said first key stage and said clock signal is applied to said first key stage.

8. The method of claim 7 wherein said clock signal is received at said integrated circuit device through a control signal input.

9. The method of claim 1 wherein said key sequence comprises a series of address signals applied to said integrated circuit during an otherwise unpermitted time period.

21. The method of claim 1 wherein said key sequence comprises an otherwise illegal address sequence.

10. A method, comprising propagating a test mode enable signal through a series of clocked key stages in an integrated circuit device in response to a common clock signal and a series of unique key signals, each configured to activate a corresponding one of the clocked key stages.

11. The method of claim 10 wherein each of said series of clocked key stages comprises a d-type flip-flop responsive to said clock signal and one of said unique key signals and wherein said step of propagating comprises successively latching said test mode enable signal in each of said d-type flip-flops in response to said clock signal and a key sequence comprising said corresponding unique key signals.

12. The method of claim 11 wherein said integrated circuit device comprises a memory device and said clock signal is applied to said memory device while a control signal for said memory device is active.

13. The method of claim 12 wherein said unique key signals comprise a series of address sets.

14. An integrated circuit, comprising test mode enable circuitry responsive to a series of key signals each configured to activate a corresponding one of a number of key stages of the test mode enable circuitry and a common clock signal for the key stages.

15. The integrated circuit of claim 14 wherein each of said key stages is configured to receive an input signal and to produce an output signal in response thereto when activated by said clock signal and the corresponding key signal for that key stage.

16. The integrated circuit of claim 15 wherein each of said key stages comprises a d-type flip-flop.

17. A computer system comprising the integrated circuit of claim 14.

18. The computer system of claim 17 wherein said integrated circuit comprises a memory device.

19. The integrated circuit of claim 15 wherein said key signals comprise a set of address signals.

20. The integrated circuit of claim 19 wherein said clock signal is derived from at least one control signal provided to said integrated circuit.