Method for characterizing interconnect timing characteristics

• US 6,005,829 A
• Filed: 05/21/1998
• Issued: 12/21/1999
• Est. Priority Date: 09/17/1996
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Conn, Robert O.
• Primary Examiner(s): MISKA, VIT W
• Application Number:
  US09/083,892
• Time in Patent Office: 579 Days
• Field of Search: 548/113, 548/118, 548/120, 327/261-267, 327/39, 327/45-47, 324/73.1, 324/76.41, 324/658, 324/681-686
• US Class Current: 368/118
• CPC Class Codes: G01R 27/04 in circuits having distributed constants , e.g. having very long conductors or involving high frequencies
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2882 Testing timing characteristics
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]

Abstract

A reference ring oscillator circuit (RROC) is used to determine timing characteristics of a test interconnect structure in an integrated circuit. The RROC includes an odd number of inverters coupled together in a ring manner and has defined test segments at which a test interconnect can be loaded. Reference timing characteristics of the unloaded RROC are determined according to a calibration method including the steps of: (a) directly measuring signal propagation delay through each segment of the RROC; (b) modeling each test segment using an RC tree type reference circuit model having reference elements; (c) simulating the reference circuit model to provide a functional relationship between two reference capacitors; (d) defining upper and lower bounds for propagation delay through the test segment in terms of the reference elements; (e) determining values for the reference capacitor elements; and (f) measuring a reference frequency of oscillation of the unloaded RROC. After calibration, a test frequency of oscillation of the RROC is measured while a test interconnect structure is loaded onto a test segment. The period of the reference frequency is subtracted from the period of the test frequency. A time difference between the two periods is attributed to increased signal propagation delay through the RROC as a result of loading the test interconnect structure onto the test segment. Based on the measured time difference and determined reference timing characteristics of the test segment, timing characteristics of the test interconnect structure are determined.

Claims

1. A method of determining interconnect timing characteristics of a test interconnect structure, the method comprising:

a. determining a first timing characteristic of a reference logic unit and a reference interconnect structure;

b. connecting the test interconnect structure to the reference interconnect structure;

c. measuring a second timing characteristic of the reference logic unit and reference interconnect structures connected to the test interconnect structure;

d. comparing the first and second timing characteristics to determine a time value; and

e. determining the interconnect timing characteristics of the test interconnect structure based on the time value and the first and second timing characteristics of the reference interconnect structure;

f. wherein the timing characteristics of the test interconnect structure represent capacitance values based on an interconnect model representative of the test interconnect structure.

2. The method of claim 1, wherein the test interconnect structure includes a programmable pass transistor.

3. A method of determining timing characteristics of a test interconnect structure, the method comprising:

a. configuring a programmable integrated circuit to include a reference oscillator that includes a reference interconnect structure;

b. measuring a first oscillation frequency of the reference oscillator;

c. connecting the test interconnect structure to the reference interconnect structure, thereby imposing a load on the reference interconnect structure;

d. measuring a second oscillation frequency of the reference oscillator, the second oscillation frequency differing from the first oscillation frequency by a frequency difference proportional to the load imposed by the test interconnect structure on the reference interconnect structure; and

e. calculating the load imposed by the test interconnect structure on the reference interconnect structure based on the frequency difference.

4. The method of claim 3, wherein the load comprises a resistance and a capacitance.

5. The method of claim 3, wherein the frequency difference is obtained by subtraction.

6. The method of claim 3, wherein the reference interconnect structure includes a reference capacitance value, the method further comprising directly measuring the reference capacitance value.

7. The method of claim 3, further comprising directly measuring a signal propagation delay through the reference interconnect structure.

8. The method of claim 3, further comprising modeling the reference interconnect structure using a reference circuit model.

9. The method of claim 3, wherein the reference interconnect structure is one of a plurality of such structures on the programmable integrated circuit.

10. The method of claim 8, wherein the reference circuit model comprises an RC tree network.