Methodology for discontinuous radio reception utilizing embedded frame length words

• US 6,005,885 A
• Filed: 12/12/1995
• Issued: 12/21/1999
• Est. Priority Date: 12/12/1995
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Intermec IP Corporation (Honeywell International Inc.)
• Inventors: Jovanovich, Alan F., Mensonides, John W., Warren, Bruce G.
• Primary Examiner(s): VO, DON NGUYEN
• Application Number:
  US08/570,982
• Time in Patent Office: 1,470 Days
• Field of Search: 375/200, 375/205, 375/206, 340/825.44, 340/825.07, 340/825.52, 455/343, 455/38.3, 455/574, 370/311, 370/401, 370/318, 370/349, 370/475, 370/465, 379/58, 379/63
• US Class Current: 375/152
• CPC Class Codes: H04B 1/707 using direct sequence modulation

Abstract

A radio receiver for direct sequence spread spectrum radio frequency (RF) signals is provided which discontinues radio reception when it is recognized that a received signal is intended for another such receiver. As a result, the receiving apparatus draws substantially less electrical current than conventional spread spectrum receivers. The apparatus provides for demodulation of an RF signal to recover digital information in the form of a transmitted message packet having a header portion and a data portion. The apparatus determines a message address and data length from the header portion. If the determined address does not correspond to the distinct apparatus address of the particular receiver, the apparatus disables the signal demodulation operation for a discrete period of time corresponding to the determined data length.

Claims

1. An apparatus for receiving radio frequency (RF) signals and having a distinct apparatus address, comprising:

means for demodulating an RF signal to recover digital information in the form of a transmitted message packet having a header portion defining a single destination address and a variable length data portion;

means for determining said destination address from said header portion;

means for determining a message packet length from said header portion; and

means for discontinuing operation of said demodulating means for an entire remaining duration of said message packet defined by said message packet length if the determined destination address does not correspond to the distinct apparatus address.

2. The receiving apparatus of claim 1, wherein said demodulating means further comprises an RF receiver and a digital match filter coupled to said RF receiver.

3. The receiving apparatus of claim 2, wherein said discontinuing means further comprises means for disabling application of RF power to said RF receiver.

4. The receiving apparatus of claim 2, wherein said discontinuing means further comprises means for disabling application of a clock signal to said digital match filter.

5. The receiving apparatus of claim 4, wherein said disabling means further comprises a logic gate having said clock signal provided to an input thereof.

6. The receiving apparatus of claim 1, wherein said determining means provides a control signal if the determined destination address does not correspond to the distinct apparatus address.

7. The receiving apparatus of claim 6, wherein said discontinuing means further comprises a power management circuit coupled to said determining means and receiving said control signal.

8. The receiving apparatus of claim 7, wherein said discontinuing means further comprises a logical AND gate having an input coupled to an output of said power management circuit.

9. The receiving apparatus of claim 1, wherein said demodulating means further comprises means for de-spreading said RF signal to recover the digital information.

10. An apparatus for receiving radio frequency (RF) signals and having a distinct apparatus address, comprising:

means for demodulating an RF signal to recover digital information in the form of a transmitted message packet having a header portion defining a single destination address and a data portion;

means for determining said single destination address from said header portion;

means for determining a message packet length from said header portion; and

means for discontinuing operation of said demodulating means if the determined destination address does not correspond to the distinct apparatus address, wherein said discontinuing means further comprises means for disabling said demodulating means for a period of time corresponding to the determined message packet length.

11. An apparatus for receiving direct sequence spread spectrum radio frequency (RF) signals and having a distinct apparatus address, comprising:

an analog RF receiver adapted to receive an RF signal;

a digital match filter coupled to said RF receiver, said digital match filter adapted to recover digital information from said RF signal in the form of a transmitted message packet having a header portion and a variable length data portion, said header portion defining a single destination address for said message packet and a length of said data portion of said message packet;

means for determining at least said destination address and said message packet length from said header portion; and

means for disabling operation of at least said analog RF receiver and said digital match filter for a period of time corresponding to the determined message packet length if the determined destination address does not correspond to the distinct apparatus address.

12. The receiving apparatus of claim 11, wherein said disabling means further comprises means for disabling application of RF power to said analog RF receiver.

13. The receiving apparatus of claim 11, wherein said disabling means further comprises means for disabling application of a clock signal to said digital match filter.

14. The receiving apparatus of claim 13, wherein said disabling means further comprises a logical AND gate having said clock signal provided to an input thereof.

15. A method for reducing electrical power usage in a direct sequence spread spectrum radio system, said radio system having a distinct apparatus address, said method comprising steps of:

demodulating an RF signal to recover digital information in the form of a transmitted message packet having a header portion defining a single destination address and a variable length data portion;

determining said message destination address and a message packet length from said header portion; and

disabling said demodulating step for an entire remaining duration of said message packet defined by said message packet length if the determined address does not correspond to the distinct apparatus address.

16. The method of claim 15, wherein said demodulating step further comprises the step of de-spreading said RF signal to remove spread spectrum modulation and recover the digital information.

17. The method of claim 15, wherein said disabling step further comprises the step of disabling application of RF power to an analog RF receiver of the radio system.

18. The method of claim 15, wherein said disabling step further comprises the step of disabling application of a clock signal to a digital match filter of the radio system.

19. A method for reducing electrical power usage in a direct sequence spread spectrum radio system, said radio system having a distinct apparatus address, said method comprising steps of:

demodulating an RF signal to recover digital information in the form of a transmitted message packet having a header portion defining a single destination address and a data portion;

determining said message destination address from said header portion;

disabling said demodulating step if the determined address does not correspond to the distinct apparatus address; and

determining a message packet length from said header portion, and said disabling step further comprises disabling said demodulating step for a time interval proportional to the determined message packet length.

20. An apparatus for receiving direct sequence spread spectrum radio frequency (RF) signals and having a distinct apparatus address, comprising:

an analog RF receiver adapted to receive an RF signal;

a digital match filter coupled to said RF receiver, said digital match filter adapted to recover digital information from said RF signal in the form of a transmitted message packet having a header portion and a data portion, said header portion defining a single destination address of said message packet and a message packet length of said data portion;

a control logic unit coupled to said RF receiver and said digital match filter, and having embedded instructions to perform the functions of;

determining at least said destination address and said message packet length from said header portion; and

disabling operation of at least said analog RF receiver and said digital match filter for a period of time corresponding to the determined message packet length if the determined destination address does not correspond to the distinct apparatus address.

21. The receiving apparatus of claim 20, wherein said control logic unit further comprises embedded instructions for disabling application of RF power to said analog RF receiver.

22. The receiving apparatus of claim 20, wherein said control logic unit further comprises embedded instructions for disabling application of a clock signal to said digital match filter.

23. The receiving apparatus of claim 22, further comprising a logical AND gate having said clock signal provided to an input thereof.

24. An apparatus for receiving radio frequency (RF) signals and having a distinct apparatus address, comprising:

an RF receiver adapted to receive an RF signal and recover digital information from said RF signal in the form of a transmitted message packet having a header portion and a variable length data portion, said header portion defining a single destination address of said message packet and a message packet length of said data portion; and

a control logic unit coupled to said RF receiver and adapted to determine at least said destination address and said message packet length from said header portion, and to disable operation of portions of said RF receiver for a period of time corresponding to the determined message packet length if the determined destination address does not correspond to the distinct apparatus address.

25. The receiving apparatus of claim 24, wherein said RF receiver further comprises a digital match filter.

26. The receiving apparatus of claim 25, wherein said control logic unit is further adapted to disable application of a clock signal to said digital match filter.

27. An apparatus for receiving direct sequence spread spectrum radio frequency (RF) signals and having a distinct apparatus address, comprising:

an analog RF receiver adapted to receive an RF signal;

a digital match filter coupled to said RF receiver, said digital match filter adapted to recover digital information from said RF signal in the form of a transmitted message packet having a header portion and a variable length data portion, said header portion defining a destination address of said message packet and a message packet length of said data portion;

a control logic unit coupled to said RF receiver and said digital match filter, and having embedded instructions to perform the functions of;

reading at least said destination address and said message packet length from said header portion;

determining a length of time to transmit said data portion from said message packet length; and

disabling operation of at least said analog RF receiver and said digital match filter for said determined length of time if the destination address of said message packet does not correspond to the distinct apparatus address.

28. An apparatus for receiving radio frequency (RF) signals and having a distinct apparatus address, comprising:

an RF receiver adapted to receive an RF signal and recover digital information from said RF signal in the form of a transmitted message packet having a header portion and a variable length data portion, said header portion defining a destination address of said message packet and a message packet length of said data portion; and

a control logic unit coupled to said RF receiver and adapted to recover at least said destination address and said message packet length from said header portion, said control logic unit reducing electrical power applied to said RF receiver for a period of time corresponding to the message packet length if the determined destination address does not correspond to the distinct apparatus address.