Phase-locked loop with protected output during instances when the phase-locked loop is unlocked

• US 6,005,904 A
• Filed: 10/16/1997
• Issued: 12/21/1999
• Est. Priority Date: 10/16/1997
• Status: Expired due to Term

• Current Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Original Assignee: Oasis Design Incorporated
• Inventors: Knapp, David J., Susanto, Tony, Trager, David S.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): JIANG, LENNY R
• Application Number:
  US08/951,796
• Time in Patent Office: 796 Days
• Field of Search: 375/376, 331/DIG. 2, 327/156, 327/159
• US Class Current: 375/376
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
• CPC Class Codes: H04L 7/04 Speed or phase control by synchronisation signals H04L7/0075 takes precedence
• CPC Class Codes: Y10S 331/02 Phase locked loop having lock indicating or detecting means

Abstract

A circuit is provided for controlling or regulating a phase-locked loop (PLL) output during times when the PLL is unlocked. Noise or corruption on the input signal of the PLL may cause the PLL output frequency to suddenly rise to match the input signal frequency. In many instances, the noise or corruption cannot be filtered by the low pass filter within the PLL. A detection circuit is coupled to receive the input signal, and discern times in which non-filterable noise occurs. The detection circuit may include a decoder which decodes, e.g., error correction coding within the input signal data stream to indicate possible instances in which the PLL will unlock. Once the detection circuit indicates an unlock condition and forwards an unlock selection signal to a multiplexer, the multiplexer chooses a frequency divided clocking signal rather than the PLL output clocking signal. The frequency divided clocking signal transitions at a rate acceptable to a digital processor, while the PLL output clocking signal during an unlock state is not acceptable. Thus, the digital processor can maintain its operating state during times when the PLL clocking signal exceeds the processor maximum operation frequency.

Claims

1. An apparatus, comprising:

a phase-locked loop coupled to receive an input signal;

a detection circuit coupled to receive the input signal and to dispatch an unlock signal if the frequency of the input signal exceeds a pre-defined amount; and

a multiplexer, upon receiving the unlock signal directly from the detection circuit, is adapted for selecting a frequency divided clocking signal produced from an output of the phase-locked loop.

2. The apparatus as recited in claim 1, wherein said detection circuit comprises a decoder.

3. The apparatus as recited in claim 1, wherein said detection circuit comprises a decoder and a counter serially coupled to one another for dispatching the unlock signal when the input signal comprises at least two successive sets of erroneous binary code.

4. The apparatus as recited in claim 3, wherein said erroneous binary code comprises a sequence of binary bits dissimilar from a pre-defined sequence of binary bits.

5. The apparatus as recited in claim 1, wherein said unlock signal is dispatched during times when the frequency exceeds a pre-defined amount.

6. The apparatus as recited in claim 1, wherein said frequency divided clocking signal is output from a clock divider circuit coupled to receive an output signal from the phase-locked loop.

7. The apparatus as recited in claim 6, wherein said clock divider circuit is coupled to divide a frequency of the output signal forwarded from the phase-locked loop.

8. The apparatus as recited in claim 7, wherein the frequency of the output signal is at least equal to the frequency of the input signal.

9. The apparatus as recited in claim 1, further comprising a digital processor coupled to receive the frequency divided clocking signal.

10. An integrated circuit for selectively controlling the operating frequency of a digital processor, comprising:

a phase-locked loop coupled to receive an input signal and, in response to the input signal, to produce an output signal;

a detection circuit coupled to receive the input signal and to dispatch an unlock signal if the frequency of the input signal exceeds a pre-defined amount;

a clock divider circuit coupled to receive the output signal and divide the frequency of the output signal to produce a frequency divided clocking signal; and

a multiplexer coupled to forward the frequency divided clocking signal to the digital processor upon receiving the unlock signal directly from the detection circuit.

11. The integrated circuit as recited in claim 10, wherein said frequency divided clocking signal transitions at a frequency which is a division of the frequency of the output signal.

12. The integrated circuit as recited in claim 10, wherein said multiplexer is coupled to receive said frequency divided clocking signal, said output signal and said unlock signal.

13. The integrated circuit as recited in claim 10, wherein said detection circuit is further coupled to dispatch a lock signal if the frequency of the input signal is less than the pre-defined amount.

14. The integrated circuit as recited in claim 13, wherein said multiplexer is coupled to forward the output signal to the digital processor upon receiving the lock signal.

15. The integrated circuit as recited in claim 10, wherein said frequency divided clocking signal is strobed at a frequency within the operating frequency of the digital processor.