Cross-linked development and deployment apparatus and method

• US 6,006,022 A
• Filed: 11/15/1996
• Issued: 12/21/1999
• Est. Priority Date: 11/15/1996
• Status: Expired due to Fees

• Current Assignee: Microsystem Synthesis Incorporated
• Original Assignee: Microsystem Synthesis Incorporated
• Inventors: Hayden, Russell David, Rhim, Hotaek, Rea, William Chester
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): PHAN, THAI Q
• Application Number:
  US08/749,456
• Time in Patent Office: 1,131 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 395/500, 395/500.02, 395/500.17, 395/500.35, 395/500.44, 395/500.47, 395/500.49, 395/702, 395/710
• US Class Current: 716/102
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A cross-linked development and deployment system that links system design, simulation, real-time emulation, integration, and in-system verification to system implementation in the field, creating final products that are field programmable systems on printed circuit boards or field programmable systems on silicon. In a preferred embodiment, hardware and software models are created and verified in an integrated co-development environment. These models can be synchronized with each other and can also be used for in-circuit emulation and in-system verification of the system under development. Once the system has gone through verification and completed system integration, the system design database that has been generated from that testing is used to program either a field programmable printed circuit board or a field programmable system on silicon. In either case, connections are embedded in the field programmable final product that enable it to link back into the integrated co-development environment so that results created by the final product can be compared with results stored in the integrated co-development environment. The final product can also be connected to the integrated co-development environment for further analysis.

Claims

1. An apparatus for providing a cross-linked development and deployment environment for electronic design automation of a system under development comprising:

a host computer having a processor and attached peripheral devices;

system control software executing in the host computer, the system control software having the ability to control synchronization;

a hardware model using actual hardware components for emulating the system under development and in communication with the host computer, the hardware model having a plurality of programmable components and being controlled by the system control software;

a software model simulating the system under development and structured to mirror the hardware model, the software model executing under the control of the host computer and the system control software;

an analyzer memory for recording machine states during execution of the hardware model, the analyzer memory being in communication with the hardware model and the host computer for synchronization with the software model;

event detection logic capable of detecting predetermined types of events occurring in the hardware model for synchronization purposes; and

a design database for storing the results recorded as the models are exercised, synchronized, and analyzed under the control of the host computer so that files can be created to program a field programmable final product for deployment.

2. The apparatus of claim 1, wherein the analyzer memory further comprises at least one circular buffer of user selectable size for recording state information such as event identifier, register contents and state indicators during the execution of the hardware model.

3. The apparatus of claim 2, wherein the event detection logic further comprises an internal clock signal source for use in creating a time stamp when recording events in the circular buffer.

4. The apparatus of claim 3, wherein the system control software further comprises a test vector generator for reading the state information recorded in the circular buffer and storing it into the design database.

5. The apparatus of claim 4, wherein the system control software further comprises synchronization logic for reading state information from the design database and inserting it into the software model to enable it to begin execution at a specified state, thereby allowing the hardware model to act as an accelerator for the software model.

6. The apparatus of claim 2, wherein the analyzer memory can be set with predetermined states in advance of execution to create a particular test case.

7. The apparatus of claim 1, wherein the host computer further comprises a connectivity file stored therein which identifies the structure of the hardware model and enables the hardware model to be reconfigured.

8. The apparatus of claim 7, wherein the hardware model can be reconfigured to do rapid-turn-prototyping.

9. The apparatus of claim 7, wherein the hardware model and software model can be executed together under the control of system control software to perform in-system verification.

10. The apparatus of claim 1, wherein the design database is used to create a field programmable final product in printed circuit form.

11. The apparatus of claim 10, wherein the field programmable final product in printed circuit form can be used as the hardware model under the control of the host computer.

12. The apparatus of claim 1, wherein the design database is used to create a field programmable final product in silicon chip form.

13. The apparatus of claim 12, wherein the field programmable final product in silicon chip form can be used as the hardware model under the control of the host computer.

14. The apparatus of claim 1, wherein the software model can be used as a virtual special bond-out clip for the hardware model.