Failover and failback system for a direct access storage device

• US 6,006,342 A
• Filed: 12/11/1997
• Issued: 12/21/1999
• Est. Priority Date: 12/11/1997
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Benhase, Micheal T., Beardsley, Brent C.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): ELISCA, PIERRE E
• Application Number:
  US08/988,887
• Time in Patent Office: 740 Days
• Field of Search: 714/5, 714/6, 714/7, 714/8, 714/9, 714/10, 714/13, 711/114, 711/120, 711/162, 370/220, 370/226
• US Class Current: 714/5.11
• CPC Class Codes: G06F 11/2092 Techniques of failing over between control units
• CPC Class Codes: G06F 11/2097 maintaining the standby controller/processing unit updated initialisation or re-synchronisation thereof G06F11/1658 and subgroups

Abstract

Disclosed is a system for handling failures in a storage controller interfacing between a plurality of host systems and direct access storage devices (DASDs). The storage controller directs data from the host systems through a first and second data paths in the storage controller to a DASD. A first processor, first non-volatile memory unit (NVS), and a first cache are associated with the first data path and a second processor, a second NVS, and a second cache are associated with the second data path. A bridge provides communication between the first processor and the second NVS and the second processor and the first NVS. During normal operations prior to a failure in the storage controller, data directed to the first data path is written in the first cache and communicated with the first processor to the second NVS via the bridge for storage in the second NVS. Data directed to the second data path is written in the second cache and communicated with the second processor to the first NVS via the bridge for storage in the first NVS. A point of failure within at least one of the first processor, first cache, and first NVS is handled by routing the data directed to the first data path to the second processor and writing the routed data to the second cache and the second NVS. Upon repairing the point of failure, the data directed to the first data path is rerouted to the first processor, wherein the rerouted data is written in the first cache and communicated with the first processor to the second NVS via the bridge for storage therein.

Claims

1. A method for handling failures in a storage controller interfacing between a plurality of host systems and direct access storage devices (DASDs), comprising the steps of:

(a) directing data from the host systems through a first and second data paths in the storage controller to a DASD, wherein a first processor, first non-volatile memory unit (NVS), and a first cache are associated with the first data path, wherein a second processor, a second NVS, and a second cache are associated with the second data path, and wherein a bridge provides communication between the first processor and the second NVS and the second processor and the first NVS, comprising the steps of;

(1) writing data directed toward the first data path in the first cache;

(2) communicating with the first processor data directed toward the first data path to the second NVS via the bridge for storage in the second NVS;

(3) writing data directed toward the second data path in the second cache;

(4) communicating with the second processor data directed toward the second data path to the first NVS via the bridge for storage in the first NVS;

(b) handling a point of failure within at least one of the first processor, first cache, and first NVS, comprising the steps of routing data directed toward the first data path to the second processor and writing the routed data to the second cache and the second NVS; and

(c) rerouting data directed to the first data path to the first processor upon repairing the point of failure, wherein the rerouted data is written in the first cache and communicated with the first processor to the second NVS via the bridge for storage therein.

2. The method of claim 1, wherein data is written to the first NVS when the data is to be written to the DASD and the data is present in the second cache, and wherein data is written to the second NVS when the data is to be written to the DASD and the data is present in the first cache.

3. The method of claim 1, wherein the step of handling a failure further comprises the steps of:

destaging the data in the second cache to the DASD; and

copying the data in the second NVS to the second cache.

4. The method of claim 1, wherein the step of rerouting data directed to the first data path upon repairing the point of failure further comprises the steps of:

destaging data directed to the second data path that was written to the second NVS during failure handling to the DASD;

destaging data that was routed from the first data path to the second processor and written to the second cache during failure handling to the DASD; and

copying data that was routed from the first data path to the second processor and written to the second NVS during failure handling to the first cache.

5. The method of claim 1, wherein the step of directing data from the host systems through the first and second data paths further comprises the steps of directing data from the first processor to a first device adaptor which accesses a DASD within a group of DASDs and directing data from the second processor to a second device adaptor which accesses a DASD within the group of DASDs, and wherein the step of routing data from the first data path to the second processor during failure handling further comprises writing the routed data to a DASD via the second device adaptor.

6. The method of claim 5, wherein there are at least two groups of DASDs and at least two first device adaptors interfacing the first processor with the DASDs and at least two second device adaptors interfacing the second processor with the DASDs, wherein each group of DASDs has a first and second device adaptor attached thereto, wherein a first group of DASDs includes a first and second logical subsystems and wherein a second group of DASDs includes a third and fourth logical subsystems, wherein the step of directing data through the first and second data paths prior to failure further comprises the steps of:

(1) directing data directed to the first logical subsystem through the first data channel to the first group of DASDs via one of the first device adaptors;

(2) directing data directed to the second logical subsystem through the second data channel to the first group of DASDs via one of the second device adaptors;

(3) directing data directed to the third logical subsystem through the first data channel to the second group of DASDs via one of the first device adaptors; and

(4) directing data directed to the fourth logical subsystem through the second data channel to the second group of DASDs via one of the second device adaptors.

7. The method of claim 6, wherein the step of routing data directed to the first data path to the second processor in the event of a point of failure further comprises the steps of:

routing data directed to the first logical subsystem to one of the second device adaptors attached to the first group of DASDs, wherein the second device adaptor writes the routed data to the first logical subsystem; and

routing data directed to the third logical subsystem to one of the second device adaptors attached to the first group of DASDs, wherein the second device adaptor writes the routed data to the third logical subsystem.

8. The method of claim 7, wherein the point of failure occurs in the first device adaptor linked to the first logical subsystem, and wherein the step of rerouting data directed to the first data path to the first processor comprises the steps of routing data directed to the first, second, and fourth logical subsystems to the second processor and second device adaptors and routing data directed to the third logical subsystem to the first processor and a first device adaptor.

9. The method of claim 8, wherein the step of rerouting the data directed to the first data path to the first processor further comprises:

destaging data directed to the first, second, and fourth logical subsystems that was written to the second NVS during failure handling to the DASD;

destaging data directed to the third logical subsystem that was routed from the first data path to the second processor and written to the second cache during failure handling to the DASD; and

copying data directed to the third logical subsystem that was routed from the first data path to the second processor and written to the second NVS during failure handling to the first cache.

10. A storage controller for interfacing between a plurality of host systems and direct access storage devices (DASDs), wherein data is transferred between the host systems and a first and second locations in the DASDs, comprising:

(a) a first cluster, including a first processor, a first non-volatile memory unit (NVS), and a first cache;

(b) a second cluster, including a second processor, a second NVS, and a second cache;

(c) a bridge providing communication between the first processor and the second NVS and the second processor and the first NVS, wherein data directed toward the first location is directed toward the first processor and written in the first cache and the second NVS, and wherein data directed to the second location is directed toward the second processor and written in the second cache and the first NVS;

(d) means, performed by the second processor, for detecting a failure in the first cluster;

(e) means for routing data directed toward the first location to the second processor and writing the routed data to the second cache and the second NVS in response to detecting a failure within the first cluster; and

(f) means for rerouting data directed toward the first location to the first processor upon repairing the failure in the first cluster, wherein the rerouted data is written in the first cache and the second NVS via the bridge.

11. The storage controller of claim 10, wherein data is written to the first NVS when the data is to be written to the DASD and the data is present in the second cache, and wherein data is written to the second NVS when the data is to be written to the DASD and the data is present in the first cache.

12. The storage controller of claim 10, wherein the means for routing data in response to detecting a failure further includes:

means, performed by the second processor, for destaging the data in the second cache to the DASD; and

means, performed by the second processor, for copying the data in the second NVS to the second cache.

13. The storage controller of claim 10, wherein the step of rerouting data directed to the first location upon repairing the failure in the first cluster further comprises:

means, performed by the second processor, for destaging data directed to the second location that was written to the second NVS during failure handling to the DASD;

means, performed by the second processor, for destaging data that was routed to the second processor and written to the second cache during failure handling to the DASD; and

means for copying data that was routed from the first data path to the second processor and written to the second NVS during failure handling to the first cache.

14. The storage controller of claim 10, further including:

a group of DASDs including the first and second locations;

a first device adaptor interfacing between the first processor and the group of DASDs, wherein data directed to the first location is directed by the first processor to the first device adaptor which writes the data to the first location; and

a second device adaptor interfacing between the second processor and the group of DASDs, wherein the data directed to the second location is directed by the second processor to the second device adaptor which writes the data to the second location, and wherein the second device adaptor writes the data directed to the first location to the first location within the group of DASDs when the data directed to the first location is routed to the second processor.

15. The storage controller of claim 14, further composing:

a second group of DASDs including a third and fourth location therein;

at least one more first device adaptor interfacing between the second group of DASDs and the first processor, wherein data directed to the third location is directed by the first processor to the first device adaptor attached to the second group of DASDs; and

at least one more second device adaptor interfacing between the second group of DASDs and the second processor, wherein data directed to the fourth location is directed by the second processor to the second device adaptor attached to the second group of DASDs, and wherein the second adaptor writes data directed to the third location to the third location when the data directed to the third location is routed to the second processor upon failure detection.

16. The storage controller of claim 15, wherein the failure occurs in the first device adaptor linked to the first location, and wherein the step of routing data directed to the first location to the second processor comprises the steps of routing data directed to the first, second, and fourth logical subsystems to the second processor and second device adaptors and routing data directed to the third location to the first processor and a first device adaptor.

17. The storage controller of claim 16, wherein the means for rerouting the data directed to the first location to the first processor further comprises:

means, performed by the second processor, for destaging data directed to the first, second, and fourth locations that was written to the second NVS during failure handling to the DASDs;

means, performed by the second processor, for destaging data directed to the third location that was routed to the second processor and written to the second cache during failure handling to the DASD; and

means for copying data directed to the third location that was routed from the first data path to the second processor and written to the second NVS during failure handling to the first cache.

18. An article of manufacture for use in programming a storage controller to direct data between host systems and direct access storage devices (DASDs), the article of manufacture comprising a storage medium having logic embodied therein that causes components of the storage controller to perform the steps of:

(a) directing data from the host systems through a first and second data paths in the storage controller to a DASD, wherein the first processor, a first non-volatile memory unit (NVS), and a first cache are associated with the first data path, wherein the second processor, a second NVS, and a second cache are associated with the second data path, and wherein a bridge provides communication between the first processor and the second NVS and the second processor and the first NVS, comprising the steps of;

(1) writing data directed toward the first data path in the first cache;

(2) communicating with the first processor data directed toward the first data path to the second NVS via the bridge for storage in the second NVS;

(3) writing data directed toward the second data path in the second cache;

(4) communicating with the second processor data directed toward the second data path to the first NVS via the bridge for storage in the first NVS;

(b) handling a point of failure within at least one of the first processor, first cache, and first NVS, comprising the steps of routing data directed toward the first data path to the second processor and writing the routed data to the second cache and the second NVS; and

(d) rerouting data directed to the first data path to the first processor upon repairing the point of failure, wherein the routed data is written in the first cache and communicated with the first processor to the second NVS via the bridge for storage therein.

19. The article of manufacture of claim 18, wherein data is written to the first NVS when the data is to be written to the DASD and the data is present in the second cache, and wherein data is written to the second NVS when the data is to be written to the DASD and the data is present in the first cache.

20. The article of manufacture of claim 18, wherein the step of handling a point of failure further comprises the steps of:

destaging with the second processor the data in the second cache to the DASD; and

copying with the second processor the data in the second NVS to the second cache.

21. The article of manufacture of claim 18, wherein the step of rerouting data directed to the first data path upon repairing the point of failure further comprises the steps of:

destaging with the second processor data directed to the second data path that was written to the second NVS during failure handling to the DASD;

destaging with the second processor data that was routed from the first data path to the second processor and written to the second cache during failure handling to the DASD; and

copying data that was routed from the first data path to the second processor and written to the second NVS during failure handling to the first cache.

22. The article of manufacture of 18, wherein the step of directing data from the host systems through the first and second data paths further comprises the steps of directing data from the first processor to a first device adaptor which accesses a DASD within a group of DASDs and directing data from the second processor to a second device adaptor which accesses a DASD within a group of DASDs, wherein the first device adaptor and the second device adaptor are attached to the group of DASDs to access data locations therein, and wherein the step of routing data from the first data path to the second processor during failure handling further comprises writing the routed data to a DASD via the second device adaptor.

23. The article of manufacture of claim 22, wherein there are at least two groups of DASDs, and at least two first device adaptors and second device adaptors, wherein at least one of the first device adaptors and one of the second device adaptors are attached to each group of DASDs, wherein a first group of DASDs includes a first and second logical subsystems and wherein a second group of DASDs includes a third and fourth logical subsystems, wherein the step of directing data through the first and second data paths prior to failure further comprises the steps of:

(1) directing data directed to the first logical subsystem through the first data channel to the first group of DASDs via one of the first device adaptors;

(2) directing data directed to the second logical subsystem through the second data channel to the first group of DASDs via one of the second device adaptors;

(3) directing data directed to the third logical subsystem through the first data channel to the second group of DASDs via one of the first device adaptors; and

(4) directing data directed to the fourth logical subsystem through the second data channel to the second group of DASDs via one of the second device adaptors.

24. The article of manufacture of claim 23, wherein the step of routing data directed to the first data path to the second processor in the event of a point of failure further comprises the steps of:

routing data directed to the first logical subsystem to one of the second device adaptors attached to the first group of DASDs, wherein the second device adaptor writes the routed data to the first logical subsystem; and

routing data directed to the third logical subsystem to one of the second device adaptors attached to the first group of DASDs, wherein the second device adaptor writes the routed data to the third logical subsystem.

25. The article of manufacture of 24, wherein the point of failure occurs in the first device adaptor linked to the first logical subsystem, and wherein the step of routing data directed to the first data path to the second processor comprises the steps of routing data directed to the first, second, and fourth logical subsystems to the second processor and second device adaptors and routing data directed to the third logical subsystem to the first processor and a first device adaptor.

26. The article of manufacture of 25, wherein the step of rerouting the data directed to the first data path to the first processor further comprises:

destaging data directed to the first, second, and fourth logical subsystems that was written to the second NVS during failure handling to the DASD;

destaging data directed to the third logical subsystem that was routed from the first data path to the second processor and written to the second cache during failure handling to the DASD; and

copying data directed to the third logical subsystem that was routed from the first data path to the second processor and written to the second NVS during failure handling to the first cache.