Pattern generator for memory burn-in and test
First Claim
1. An address generator comprising:
- shift register means, the shift register means including n bit positions, the n bit positions for storing n bits and shifting the n bits out of the shift register, the n bits being capable of being in a plurality of patterns;
counter means coupled to the shift register means, the counter means having a value that is incremented in response to a particular pattern of the plurality of patterns; and
complement means coupled to the shift register means and the counter means, the complement means for providing a complement of at least a portion of the n bits shifted out of the shift register in response to the value in the counter means.
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Accused Products
Abstract
A system and method for testing of a memory during burn-in is disclosed. In one aspect, the method and system include an address generator. The address generator includes a shift register means. The shift register includes n bit positions. The n bit positions are for storing n bits. The n bits are capable of being in a plurality of patterns. The address generator further includes a counter coupled to the shift register means. The counter includes a value that is incremented in response to a particular pattern of the plurality of patterns. The address generator has a complement mechanism coupled to the shift register and the counter which provides a complement of at least a portion of the n bits stored in the n bit positions in response to the value in the counter. In another aspect, the method and system comprise the address generator previously discussed coupled to the memory undergoing testing. In this aspect, the method and system further have a data generator coupled to the address generator and the memory and compare circuitry coupled to the memory and the data generator. In this aspect, a fail is detected when data from the data generator does not match data stored in the memory.
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Citations
32 Claims
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1. An address generator comprising:
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shift register means, the shift register means including n bit positions, the n bit positions for storing n bits and shifting the n bits out of the shift register, the n bits being capable of being in a plurality of patterns; counter means coupled to the shift register means, the counter means having a value that is incremented in response to a particular pattern of the plurality of patterns; and complement means coupled to the shift register means and the counter means, the complement means for providing a complement of at least a portion of the n bits shifted out of the shift register in response to the value in the counter means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 19, 20, 21, 22, 23)
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8. A system for providing testing during burn-in of a memory comprising:
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an address generator comprising; shift register means, the shift register means including n bit positions, the n bit positions for storing n bits and shifting the n bits out of the shift register, the n bits being capable of being in a plurality of patterns; counter means coupled to the shift register means, the counter means having a value that is incremented in response to a particular pattern of the plurality of patterns; and complement means coupled to the shift register means and the counter means, the complement means for providing a complement of at least a portion of the n bits shifted out of the shift register in response to the value in the counter means; a data generator coupled to the address generator and the memory; and compare circuitry coupled to the memory and the data generator; wherein a fail is detected when data from the data generator does not match data read from the memory. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
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17. A method for providing an address generator comprising the steps of:
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providing shift register means, the shift register means including n bit positions, the n bit positions for storing n bits and shifting the n bits out of the shift register, the n bits being capable of being in a plurality of patterns; providing counter means coupled to the shift register means, the counter means having a value that is incremented in response to a particular pattern of the plurality of patterns; and providing complement means coupled to the shift register means and the counter means, the complement means for providing a complement of at least a portion of the n bits shifted out of the shift register in response to the value in the counter means. - View Dependent Claims (18)
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24. A method for providing testing during burn-in of a memory comprising the steps of:
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providing an address generator, the step of providing an address generator further comprising the steps of; providing shift register means, the shift register means including n bit positions, the n bit positions for storing n bits and shifting the n bits out of the shift register, the n bits being capable of being in a plurality of patterns; providing counter means coupled to the shift register means, the counter means having a value that is incremented in response to a particular pattern of the plurality of patterns; and providing complement means coupled to the shift register means and the counter means, the complement means for providing a complement of at least a portion of the n bits shifted out of the shift register in response to the value in the counter means; providing a data generator coupled to the address generator and the memory; and providing compare circuitry coupled to the memory and the data generator; wherein a fail is detected when data from the data generator does not match data read from the memory. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32)
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Specification