High speed pattern generating method and high speed pattern generator using the method

• US 6,006,349 A
• Filed: 03/26/1997
• Issued: 12/21/1999
• Est. Priority Date: 07/26/1995
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Fujisaki, Kenichi
• Primary Examiner(s): Nguyen, Hoa T.
• Application Number:
  US08/809,632
• Time in Patent Office: 1,000 Days
• Field of Search: 714/738, 714/739, 714/742, 714/743, 714/744, 714/718, 714/724, 714/728, 714/730, 714/731, 714/733, 714/734, 375/362, 324/73.1
• US Class Current: 714/738
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/318307 computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
• CPC Class Codes: G06F 11/27 Built-in tests

Abstract

A high speed pattern generating method by which a pattern signal having a speed higher than conventional speed can be generated using a sequence control part operating at a speed equivalent to a conventional speed and a high speed pattern generator for materializing the method are provided. A high speed pattern signal having a speed multiple of the number of multiplexing against an operation speed of the sequence control part is generated by generating multi-phase sub patterns from a plurality of sub pattern generating parts and by taking out for multiplexing the multi-phase sub patterns one phase by one phase by a multiplexing circuit. Further, an instruction memory of a pattern generator is uniquely arranged to materialize the high speed pattern generating method.

Claims

1. A high speed pattern generator comprising:

a pattern generator having a sequence control part and a pattern generating part, the sequence control part including an instruction memory and an address converting part, wherein

the instruction memory is divided into a first instruction memory in which sequence control instructions are stored and a second instruction memory comprising a plurality of sub-pattern generating instruction storage areas in which a plurality of sub-pattern generating instructions are stored respectively;

an address signal for accessing the first instruction memory is supplied to the second instruction memory via the address converting part; and

the address converting part is arranged such that when an address value of the address signal for accessing to the first instruction memory is changed toward a value incremented by one, the address converting part supplies the address signal the address value of which has been changed to the second instruction memory, and when an address value of the address signal for accessing to the first instruction memory is changed to a value other than a value incremented by one, the address converting part converts the address signal to a converted address signal having a value in which a predetermined value is added to an address value of such a preceding address signal which is in the immediately preceding cycle of the address signal for accessing to the first instruction memory, and supplies the thus converted address signal to the second instruction memory.

2. The high speed pattern generator according to claim 1 wherein said address converting part comprises:

address delay means for delaying by one cycle the address signal for accessing to said first instruction memory;

selector means for selecting and taking out either one of a delayed address signal delayed by said address delay means and an address signal which does not pass through said delay means; and

adding means for adding, when said selector means selects the delayed address signal delayed by said delay means, a predetermined value to the selected delayed address signal.

3. The high speed pattern generator according to claim 2 wherein a control signal of logical "0" is outputted when the address value of the address signal for accessing to said first instruction memory is changed toward a value incremented by one is detected, and a control signal of logical "1" is outputted when the address value of the address signal for accessing to said first instruction memory is changed to a value other than a value incremented by one is detected, said control signal of logical "1" controlling said selector means forming said address converting part so that said selector means selects the delayed address signal outputted from said address delay means, and said adding means adds said control signal of logical "1" to the most significant bit side of the selected delayed address signal to execute an address conversion.

4. The high speed pattern generator according to claim 3, further comprising:

address delay means for delaying by one cycle a converted address outputted from said address converting table; and

selector means for selecting either one of a delayed address delayed by said address delay means and an address signal for accessing to said first instruction memory to supply the selected one to said second instruction memory,

and wherein said selector means supplies, when an address value of the address signal for accessing to said first instruction memory is changed toward a value incremented by one, the address signal the address value of which has been changed to said second instruction memory, and supplies, when an address value of said first instruction memory is changed to a value other than a value incremented by one, a delayed address signal delayed by said address delay means to said second instruction memory.

5. The high speed pattern generator according to claim 4, further comprising a control logic circuit for controlling said selector means, when detects that a value of the address signal for accessing to said first instruction memory is changed toward a value incremented by one, so that said selector means selects the address signal for accessing to said first instruction memory and supplies the selected address signal to said second instruction memory, and for controlling said selector means, when detects that a value of the address signal for accessing to said first instruction memory is changed to a value other than a value incremented by one, so that said selector means selects the converted address outputted from said address converting table and supplies the selected converted address to said first instruction memory.

6. A high speed pattern generating method for generating test pattern signals at high speed from a pattern generator which comprises a sequence control part and a pattern generating part and generates a test pattern signal from said pattern generating part in accordance with a pattern generating instruction read out from an instruction memory provided in said sequence control part, said test pattern signal being applied to a device under test for testing the operation thereof, said method comprising the steps of:

providing N sub-pattern generating instruction storage areas for storing N sub-pattern generating instructions in said instruction memory, which is provided in said sequence control part, where N is an integer greater than or equal to 2;

supplying said N-sub-pattern generating instructions read out from said N sub-pattern generating instruction storage areas to N sub-pattern generating part which are provided in said N sub-pattern generating part to receive corresponding one of the respective N sub-pattern generating instructions thus supplied thereto, respectively;

generating a multi-N-phase pattern signal comprising the N sub-pattern signals having different phases generated from said N sub-pattern generating parts in accordance with the N sub-pattern generating instructions supplied thereto, respectively, said multi-N-phase pattern signal being distributed in phases and in the sequence to be applied to said device under test; and

time division multiplexing by 1/N said multi-N-phase pattern signal using a multiplexing circuit thereby generating the high speed pattern signal having an increased speed multiplexed by N, wherein

said instruction memory is divided into a first instruction memory in which sequence control instructions and an address converting table are stored, and a second instruction memory comprising a plurality of pattern generating instruction storage areas and

said address converting table converts, when an address value of the address signal for accessing to said first instruction memory is changed toward a value other than a value incremented by one in accordance with a sequence control instruction, the address value of said first instruction memory into which that sequence control instruction is stored into an address value sequentially decremented by one from the last address of said second instruction memory and outputs the converted address signal, and supplies, when and address value of the address signal for accessing to said first instruction memory is changed toward a value incremented by one, the address signal as it is to said second instruction memory, and supplies, when an address value of the address signal for accessing to said first instruction memory is changed to a value other than a value incremented by one, the converted address outputted from said address converting table to said second instruction memory.

7. A high speed pattern generating method for generating test pattern signals at high speed, being characterized by the steps of:

outputting from an instruction memory a pattern generating instruction having an argument for prescribing a plurality of sub patterns following a main pattern;

generating a main pattern from a main pattern generating part in accordance with the pattern generating instruction;

supplying said main pattern generated from said main pattern generating part to a plurality of sub pattern generating parts;

changing said main pattern in said plurality of sub pattern generating parts in accordance with said arguments;

delaying said main pattern thereby to generate a plurality of sub patterns subsequent to said main pattern in the same phase as that of said main pattern; and

time division multiplexing said main pattern and said plurality of sub patterns in a multiplexing circuit, and taking out the time division multiplexed patterns so that high speed patterns changing in accordance with a predetermined pattern generation sequence are generated.

8. A high speed pattern generator used in a semiconductor device testing apparatus for testing the operation of a device under test by generating a test pattern signal from a pattern generating part in accordance with pattern generating instructions read out from an instruction memory provided in a sequence control part and by applying the test pattern signal to the device under test,

said high speed pattern generator being characterized in that:

a main pattern generating instruction for generating a main pattern and arguments for prescribing a plurality of patterns to be generated in a predetermined sequence subsequent to the main pattern are read out from said instruction memory;

the main pattern is generated from said main pattern generating part in accordance with said read out main pattern generating instruction;

the main pattern generated from said main pattern generating part is supplied to a plurality of sub pattern generating parts;

a plurality of sub patterns corresponding to the plurality of patterns to be generated in the predetermined sequence subsequent to the main pattern are generated in accordance with said arguments in said plurality of sub pattern generating parts; and

said plurality of sub patterns and said main pattern are time division multiplexed in a multiplexing circuit so that high speed patterns having an increased speed in which the number of multiplexing in said multiplexing circuit is multiplied by the speed of reading out said pattern generating instructions are generated.

9. The high speed pattern generator according to claim 8, being characterized in that the main pattern generated from said main pattern generating part is delayed by an amount of delay time equivalent to that in said sub pattern generating parts so that the phase of said main pattern and the phases of the sub patterns generated from said plurality of sub pattern generating parts are matched by this delay operation, and said main pattern and said sub patterns the phases of which are matched with one another are supplied to said multiplexing circuit.

10. A high speed pattern generator comprising:

a sequence control part; and

a pattern generating part, wherein said sequence control part comprises;

an instruction memory which comprises a first instruction memory storing sequence control instructions and a second instruction memory having N sub-pattern generating instruction storage areas storing N sub-pattern generating instructions, where N is an integer greater than or equal to 2;

a program counter generating an address signal accessing said first instruction memory; and

an address converting part supplied with the address signal from said program counter and supplying a converted address signal to said second instruction memory;

said address converting part being arranged such that when an address value of the address signal accessing said first instruction memory is changed to a value incremented by one, said address converting part supplies the address signal, the address value of which has been changed to said second instruction memory, and

when an address value of the address signal accessing said first instruction memory is changed to a value other than a value incremented by one, said address converting part converts the address signal to an address signal having a value in which a predetermined value is added to an address in an immediately preceding cycle of the address signal accessing said first instruction memory, and supplies the converted address signal to said second instruction memory.

11. The high speed pattern generator according to claim 10, wherein said address converting part comprises:

address delay means for delaying by one cycle the address signal for accessing said first instruction memory;

selector means for selecting and taking out either one of a delayed address signal delayed by said address delay means and an address signal which does not pass through said delay means; and

adding means for adding, when said selector means selects the delayed address signal delayed by said delay means, a predetermined value to the selected delayed address signal.

12. The high speed pattern generator according to claim 11, further comprising a control logic circuit which detects the address value of the address signal and outputs a control signal of logical "Y" when the address value is a value incremented by one, and a control signal of logical "1" when the address value is a value other than the value incremented by one, wherein

said selector means selects the delayed address signal output from said address delay means when said control signal of logical "1" is supplied thereto, and

said adding means adds said control signal of logical "V" to a most significant bit side of the selected delayed address signal to execute an address conversion.

13. The high speed pattern generator according to claim 12, further comprising:

address delay means for delaying by one cycle a converted address signal output in accordance with said address converting table; and

selector means for selecting either one of the delayed converted address signal delayed by said address delay means and an address signal for accessing said first instruction memory to supply the selected one to said second instruction memory,

wherein said selector means supplies, when an address value of the address signal for accessing said first instruction memory is changed to a value incremented by one, the address signal, the address value of which has been changed to said second instruction memory, and supplies, when an address value of said first instruction memory is changed to a value other than a value incremented by one, the delayed converted address signal delayed by said address delay means to said second instruction memory.

14. A high speed pattern generator comprising:

a sequence control part;

a pattern generating part; and

a multiplexing circuit, wherein said sequence control part comprises;

a first instruction memory having a sequence control instruction storage area storing sequence control instructions and an address converting table storage area storing an address converting table,

a second instruction memory having N sub-pattern generating instruction storage areas storing respective one of sub-pattern generating instructions, respectively, where N is an integer greater than or equal to 2, and

a selector, wherein

said address converting table storage area of said first instruction memory converts in accordance with said address converting table, when an address value of the address signal for accessing said first instruction memory is changed to a value other than a value incremented by one, which change is caused by a sequence control instruction, the address value of said address signal for said first instruction memory which corresponds to the address in which said sequence control instruction is stored into a converted address signal which has an address value with sequential decrement by one from a last address of said second instruction memory, and outputs the converted address signal, and

said selector supplies, when an address value of the address signal for accessing said first instruction memory is changed to a value incremented by one, the address signal for the first instruction memory to said second instruction memory, and supplies, when the change in the address value of the address signal for accessing said first instruction memory is changed to a value other than a value incremented by one, the converted address signal output from said address converting table storage area to said second instruction memory.

15. The high speed pattern generator according to claim 14, further comprising a control logic circuit controlling said selector means, when it is detected that a value of the address signal for accessing said first instruction memory is changed to a value incremented by one, so that said selector means selects the address signal for accessing said first instruction memory and supplies the selected address signal to said second instruction memory, and controlling said selector means, when it is detected that a value of the address signal for accessing said first instruction memory is changed to a value other than a value incremented by one, so that said selector means selects the converted address signal output from said address converting table and supplies the selected converted address signal to said first instruction memory.

16. A high speed pattern generating method comprising the steps of:

outputting from an instruction memory a main pattern generating instruction and N arguments for prescribing N sub-patterns which are to be generated subsequent to the main pattern, respectively, where N is an integer greater than or equal to 2;

generating a main pattern by a main pattern generating part in accordance with the main pattern generating instruction;

supplying said main pattern generated from said main pattern generating part to N sub-pattern generating parts, respectively;

supplying respective one of said N arguments from said instruction memory to corresponding one of said N sub-pattern generating parts, respectively;

generating N sub-patterns by the N sub-pattern generating parts by changing said main pattern in accordance with the argument supplied thereto, respectively;

delaying said main pattern to match a main pattern phase with the phases of said N sub-patterns, which are generated to be subsequent to said main pattern; and

time division multiplexing by 1/N said main pattern and said N sub-patterns in a multiplexing circuit; and

removing the time division multiplexed patterns as an output pattern signal changing in accordance with a predetermined pattern generation sequence with an increased speed multiplexed by N.

17. A high speed pattern generator comprising:

a sequence control part;

a pattern generating part; and

a multiplexing circuit, wherein

said sequence control part includes an instruction memory storing a main pattern generating instruction generating a main pattern and arguments prescribing N sub-patterns to be generated in a predetermined sequence subsequent to the main pattern, where N is an integer greater than or equal to 2,

said pattern generating part comprises a main pattern generating part generating a main pattern in accordance with the main pattern generating instructions read out from the instruction memory and N sub-pattern generating parts supplied corresponding to one of the respective arguments, respectively,

each of said N sub-pattern generating parts is further supplied with the main pattern generated by said main pattern generating part so that N sub-patterns corresponding to the plurality of patterns to be generated in the predetermined sequence subsequent to the main pattern are generated in accordance with said arguments by said N sub-pattern generating parts, and

said multiplexing circuit performs time division multiplexing by 1/N onto said N sub-patterns and said main pattern so that high speed patterns having an increased speed multiplied by N are generated.

18. The high speed pattern generator according to claim 17, wherein said pattern generating part further comprises a pattern delay circuit delaying the main pattern generated from said main pattern generating part by an amount of delay time equivalent to that in said sub-pattern generating parts so that a phase of said main pattern and phases of the N sub-patterns generated from said N sub-pattern generating parts are matched by the delay operation and said main pattern and said sub-patterns, the phases of which are matched with one another, are supplied to said multiplexing circuit.

19. A high speed pattern generator comprising:

a sequence control part which includes,

an instruction memory,

a program counter supplying an address signal to said instruction memory, and

an address converting part;

a pattern generating part; and

a multiplexing part;

said instruction memory comprising;

a first instruction memory having a sequence control instruction storage area storing sequence control instructions; and

a second instruction memory having N sub-pattern generating instruction storage areas, where N is an integer equal to or greater than 2, storing N-phase sub-pattern generating instructions capable of providing N-phase sub-patterns; and

said first instruction memory is accessed with an address signal supplied thereto from the program counter deriving a sequence control instruction so that the read out sequence control instruction determines an address to be accessed next in the instruction memory,

said second instruction memory is accessed with an address signal supplied thereto from the program counter controlling a readout sequence of the N-phase sub-pattern generating instructions from said N sub-pattern generating instruction storage areas,

said address converting part receiving the address signals from said program counter is arranged such that when an address value of one address signal supplied thereto has a value incremented by one from that of a previous one address signal supplied thereto in an immediately preceding one access cycle, said address converting part supplies said one address signal supplied thereto to said second instruction memory, and

when an address value of one address signal supplied thereto has a value other than the value incremented by one from that of a previous one address signal supplied thereto in immediately preceding one access cycle, said address converting part converts said previous one address signal into a converted address signal by adding thereto a predetermined value and supplies the converted address signal to said second instruction memory.

20. The high speed pattern generator according to claim 19, wherein said pattern generating part comprises:

N-phase sub-pattern generating parts which are supplied with N-phase sub-pattern generating instructions and generate N-phase sub-patterns.

21. The high speed pattern generator according to claim 20, wherein said multiplexing part comprises:

N flip-flop circuits, to which the N-phase sub-patterns are coincidentally input from said N-phase sub-pattern generating parts, respectively, and which takes therein the supplied N-phase sub-patterns in a period of a first clock which is used for reading out of the sub-pattern generating instructions from the sub-pattern generating instruction storage areas; and

a multiplexer, to which the thus taken N-phase sub-patterns are input from the N flip-flop circuits, and which sequentially switches said N-phase sub-patterns in response to a second clock having a period of 1/N of that of said first clock, to thereby obtain a high speed pattern signal having an increased frequency multiplied by N than that of the first clock.

22. The high speed pattern generator according to claim 19, wherein said address converting part comprises:

an address delay unit delaying by one cycle the address signal to be supplied from said program counter to said first instruction memory and outputting a previous address signal;

a selector unit selecting and taking out either one of a delayed address signal delayed by said address delay means and an address signal which does not pass through said delay means; and

adding means for adding, when said selector means selects the delayed address signal delayed by said delay means, a predetermined value to the selected delayed address signal.