Bitstream decoding apparatus with reduced error correction processing and decoding method

• US 6,006,352 A
• Filed: 06/26/1997
• Issued: 12/21/1999
• Est. Priority Date: 06/27/1996
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kitabatake, Osamu
• Primary Examiner(s): De Cady, Albert
• Assistant Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US08/883,599
• Time in Patent Office: 908 Days
• Field of Search: 714/752, 714/700, 714/775, 714/798, 714/789, 360/26, 360/751
• US Class Current: 714/752
• CPC Class Codes: H04J 3/0608 Detectors therefor, e.g. correlators, state machines
• CPC Class Codes: H04N 19/89 involving methods or arrangements for detection of transmission errors at the decoder
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/43072 of multiple content streams on the same device
• CPC Class Codes: H04N 21/44209 Monitoring of downstream path of the transmission network originating from a server, e.g. bandwidth variations of a wireless network arrangements for maintenance or administration in data switching networks involving bandwidth and capacity management H04L41/0896
• CPC Class Codes: H04N 5/04 Synchronising for television systems using pulse code modulation H04N7/56
• CPC Class Codes: H04N 5/06 Generation of synchronising signals

Abstract

A decoding apparatus and a decoding method are capable of minimizing degradation of the quality of images and sounds when a synchronous signal error occurs. The decoding apparatus includes a frame counter for receiving a bit stream, a synchronous pattern detector, a data error check unit, a synchronous detector, and a frame error determination unit. A synchronous detection error occurrence signal produced by the synchronous detector is not output to an external error processing circuit but is directly transmitted to the frame error determination unit. Even when the timing of an output synchronous pattern detection signal from the synchronous pattern detector and the timing of an output frame position signal from the frame counter do not match each other and a frame synchronous abnormality occurs, if the data itself is normal then decoding processing is executed without performing any error correction processing.

Claims

1. A decoding apparatus, comprising:

synchronous pattern detecting means for receiving a bit stream, detecting a synchronous pattern of the bit stream, and producing and outputting a synchronous pattern detection signal;

frame counter means which is reset by a predetermined synchronous detection signal, starts counting the bit stream in accordance with the synchronous pattern detection signal, and produces and outputs a frame position signal;

synchronous detecting means for receiving the synchronous pattern detection signal and the frame position signal, producing and outputting the predetermined synchronous detection signal if timings of the synchronous pattern detection signal and the frame position signal match each other, and producing and outputting a synchronous error occurrence signal if the timings do not match each other;

a data error check unit for receiving the bit stream, performing error check for data of the bit stream, and producing and outputting a data error occurrence signal if an error is present in the data; and

frame error determining means for receiving the synchronous error occurrence signal and the data error occurrence signal and outputting a frame error occurrence signal to an external apparatus,

wherein when the error check yields a normal result even if an abnormality occurs in frame synchronization and generates a synchronous error, decoding processing is executed without performing any error correction processing.

2. A decoding method for decoding a sequentially input bit stream, comprising the steps of:

a first step of detecting a synchronous pattern in a unit frame of a bit stream and producing a first synchronous pattern detection signal corresponding to the synchronous pattern;

a second step of starting counting the bit stream in accordance with the first synchronous pattern detection signal and producing a frame position signal for identifying a position of the unit frame of the bit stream;

a third step of detecting the synchronous pattern in a next subsequent unit frame and producing a second synchronous pattern detection signal corresponding to the synchronous pattern;

a fourth step of determining whether a first timing of the frame position signal and a second timing of the second synchronous pattern detection signal match each other, wherein upon determining that the first and second timings match each other, returning to the first step and repeatedly executing the first through fourth steps for each unit frame of the sequentially input bit stream, and wherein upon determining that the first and second timings do not match each other, advancing to a fifth step;

the fifth step of checking, if it is determined in the fourth step that the first and second timings do not match each other, whether a corresponding unit frame contains a data error; and

a sixth step of performing decoding processing by processing the corresponding unit frame as a normal frame if no data error exists in the fifth step.

3. A decoding method for decoding a sequentially input bit stream as claimed in claim 2, wherein the sixth step further comprises outputting a frame error occurrence signal only if a data error is found in the fifth step and if the first and second timings do not match each other.