Method for simultaneous formation of contacts between metal layers and fuse windows in semiconductor manufacturing
First Claim
1. A method for simultaneous fabrication of an interlevel metal contact and a fuse window consisting of the steps of:
- a) providing a semiconductor substrate having an InterLevel Dielectric layer;
said substrate having a device area with a first metal layer over said InterLevel Dielectric layer and a fuse area with a polysilicon fuse buried within said InterLevel Dielectric layer;
b) forming an anti-reflective coating on said first metal layer;
c) patterning said first metal layer and said anti-reflective coating to form a first metal line;
d) forming an InterMetal Dielectric layer over said InterLevel Dielectric layer and said first metal line;
e) patterning said InterMetal Dielectric layer, said InterLevel Dielectric layer, and said anti-reflective coating to simultaneously open a via hole extending partially into the anti-reflective coating and a fuse window opening extending into said InterLevel Dielectric layer without exposing said fuse;
said via hole and said fuse window having sidewalls and bottoms;
f) forming an adhesion layer over said InterMetal Dielectric layer, said anti-reflective coating, and said InterLevel Dielectric;
g) blanket depositing a Tungsten layer on said adhesion layer;
h) anisotropically etching said Tungsten layer;
said etch stopping on said adhesion layer;
thereby forming a W-plug in said via hole and a W-ring on said sidewalls of said fuse window opening;
said W-ring having an inside wall;
i) forming an upper metal layer on said adhesion layer, said W-plug, and said W-ring;
j) patterning said upper metal layer using an anisotropic etch to form a upper metal line contacting said W-plug;
said anisotropic etch forming an upper metal ring on said inside wall of said W-ring;
whereby said upper metal ring and said W-ring form a moisture barrier guard ring;
k) forming a passivation layer over said upper metal layer, said InterMetal Dielectric layer, and said InterLevel Dielectric layer;
l) forming a dielectric layer on said passivation layer; and
m) patterning said dielectric layer and said passivation layer;
thereby extending said fuse window through said passivation layer.
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Accused Products
Abstract
A method for simultaneous fabrication of an interlever metal contact and a fuse window reducing the number of masking steps required while providing a high yield for the fuse. A semiconductor substrate is provided having a device area with a first metal layer over an InterLevel Dielectric layer and a fuse area with a polysilicon fuse buried within the InterLevel Dielectric layer. A thick anti-reflective coating is formed on the first metal layer. The first metal layer and the anti-reflective coating are patterned to form a first metal line. An InterMetal Dielectric layer is formed over the InterLevel Dielectric layer and the first metal line. The InterMetal Dielectric layer, the InterLevel Dielectric layer, and the anti-reflective coating are patterned, simultaneously opening a via hole extending partially into the anti-reflective coating and a fuse window opening extending into the InterLevel Dielectric layer without exposing the fuse. An adhesion layer is formed over the InterMetal Dielectric layer. A Tungsten layer is blanket deposited on the adhesion layer and anisotropically etched, forming a W-plug in the via hole and a W-ring on the sidewalls of the fuse window opening. An upper metal layer is formed on the adhesion layer, the W-plug, and the W-ring and patterned to form an upper metal line. This etch also forms an upper metal ring on the inside wall of the W-ring. A passivation layer and a dielectric layer are formed and patterned to extend the fuse window opening through the passivation layer without exposing the fuse.
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Citations
18 Claims
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1. A method for simultaneous fabrication of an interlevel metal contact and a fuse window consisting of the steps of:
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a) providing a semiconductor substrate having an InterLevel Dielectric layer;
said substrate having a device area with a first metal layer over said InterLevel Dielectric layer and a fuse area with a polysilicon fuse buried within said InterLevel Dielectric layer;b) forming an anti-reflective coating on said first metal layer; c) patterning said first metal layer and said anti-reflective coating to form a first metal line; d) forming an InterMetal Dielectric layer over said InterLevel Dielectric layer and said first metal line; e) patterning said InterMetal Dielectric layer, said InterLevel Dielectric layer, and said anti-reflective coating to simultaneously open a via hole extending partially into the anti-reflective coating and a fuse window opening extending into said InterLevel Dielectric layer without exposing said fuse;
said via hole and said fuse window having sidewalls and bottoms;f) forming an adhesion layer over said InterMetal Dielectric layer, said anti-reflective coating, and said InterLevel Dielectric; g) blanket depositing a Tungsten layer on said adhesion layer; h) anisotropically etching said Tungsten layer;
said etch stopping on said adhesion layer;
thereby forming a W-plug in said via hole and a W-ring on said sidewalls of said fuse window opening;
said W-ring having an inside wall;i) forming an upper metal layer on said adhesion layer, said W-plug, and said W-ring; j) patterning said upper metal layer using an anisotropic etch to form a upper metal line contacting said W-plug;
said anisotropic etch forming an upper metal ring on said inside wall of said W-ring;
whereby said upper metal ring and said W-ring form a moisture barrier guard ring;k) forming a passivation layer over said upper metal layer, said InterMetal Dielectric layer, and said InterLevel Dielectric layer; l) forming a dielectric layer on said passivation layer; and m) patterning said dielectric layer and said passivation layer;
thereby extending said fuse window through said passivation layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for simultaneous fabrication of an interlevel metal contact and a fuse window consisting of the steps of:
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a) providing a semiconductor substrate having an InterLevel Dielectric layer;
said substrate having a device area with a first metal layer over said InterLevel Dielectric layer and a fuse area with a polysilicon fuse buried within said InterLevel Dielectric layer at a depth of at least 1 μ
m;b) forming an anti-reflective coating on said first metal layer; c) patterning said first metal layer and said anti-reflective coating to form a first metal line; d) forming an InterMetal Dielectric layer over said InterLevel Dielectric layer and said first metal line; e) patterning said InterMetal Dielectric layer, said InterLevel Dielectric layer, and said anti-reflective coating to simultaneously open a via hole extending partially into the anti-reflective coating and a fuse window opening extending into said InterLevel Dielectric layer to a depth less than half the depth of said fuse;
said fuse window having sidewalls and bottoms;f) forming an adhesion layer over said InterMetal Dielectric layer, said anti-reflective coating, and said InterLevel Dielectric; g) blanket depositing a Tungsten layer on said adhesion layer; h) anisotropically etching said Tungsten layer;
said etch stopping on said adhesion layer;
thereby forming a W-plug in said via hole and a W-ring on said sidewalls of said fuse window opening;
said W-ring having an inside wall;i) forming an upper metal layer on said adhesion layer, said W-plug, and said W-ring; j) patterning said upper metal layer using an anisotropic etch to form an upper metal line contacting said W-plug;
said anisotropic etch forming an upper metal ring on said inside wall of said W-ring;k) forming a passivation layer over said upper metal layer, said InterMetal Dielectric layer, and said InterLevel Dielectric layer; l) forming a dielectric layer on said passivation layer; and m) patterning said dielectric layer and said passivation layer;
thereby extending said fuse window through said passivation layer without exposing said fuse. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification