Floating gate avalanche injection MOS transistors with high K dielectric control gates

• US 6,008,091 A
• Filed: 01/27/1998
• Issued: 12/28/1999
• Est. Priority Date: 01/27/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Kizilyalli, Isik C., Roy, Pradip Kumar, Gregor, Richard William
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): GUERRERO, MARIA F
• Application Number:
  US09/014,030
• Time in Patent Office: 700 Days
• Field of Search: 438/240, 438/593, 438/757, 438/266, 438/261, 438/594, 257/325, 257/316
• US Class Current: 438/261
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence

Abstract

The specification describes intergate dielectrics between the floating silicon gate and the control silicon gate in MOS memory devices. The intergate dielectrics are composite structures of SiO₂ --Ta₂ O₅ --SiO₂ with the first SiO₂ layer grown on the floating gate,, and all layers preferably produced in situ in an LPCVD reactor. After formation of the composite SiO₂ --Ta₂ O₅ --SiO₂ dielectric, it is annealed at low pressure to densify the SiO₂ layers. Electrical measurements show that the charge trap density in the intergate dielectric is substantially lower than in layered dielectrics produced by prior techniques.

Claims

1. Method for the manufacture of a MOS silicon device comprising the steps of:

a. forming a first dielectric layer on a silicon substrate,

b. forming a silicon floating gate on the first dielectric layer,

c. forming a second dielectric layer on the silicon floating gate, and

d. forming a silicon control gate on the second dielectric layer, the invention characterized in the second dielectric layer is a composite layer of SiO₂ --Ta₂ O₅ --SiO₂ formed by the steps of;

i. growing a first SiO₂ layer on the silicon floating gate, said first SiO₂ layer having a thickness in the range 10-30 Angstroms,

ii. depositing a layer of Ta₂ O₅ on the first SiO₂ layer, said layer of Ta₂ O₅ having a thickness in the range 30-100 Angstroms, and

iii. depositing a second layer of SiO₂ over said layer of Ta₂ O₅ said second layer of SiO₂ having a thickness in the range 5-30 Angstroms, the invention further characterized in that the overall thickness of the SiO₂ --Ta₂ O₅ --SiO₂ composite layer is in the range 45-100 Angstroms.

2. The method of claim 1 further including the step of annealing the SiO₂ --Ta₂ O₅ --SiO₂ composite layer at a temperature in the range 550-750°

C.

3. The method of claim 2 wherein the steps i-iii are carried out in a LPCVD reactor and each step is carried out in situ.

4. The method of claim 3 wherein the silicon control floating gate and the silicon gate are polysilicon.

5. The method of claim 4 wherein the first dielectric layer is SiO₂.

6. Method for the manufacture of an MOS silicon device comprising the steps of:

a. forming a first dielectric layer on a silicon substrate,

b. forming a silicon floating gate on the first dielectric layer,

c. forming a second dielectric layer on the silicon floating gate, and

d. forming a silicon control gate on the second dielectric layer, the invention characterized in the second dielectric layer is a composite layer of SiO₂ --Ta₂ O₅ --SiO₂ formed by the steps of;

i. placing the silicon substrate in a LPCVD reactor,

ii. heating the silicon substrate to a temperature in the range 700-950°

C.,

iii. growing a first SiO₂ layer on the silicon floating gate in an atmosphere comprising oxygen at a pressure in the range 0.7-1.0 Torr to produce a SiO₂ layer having a thickness in the range 10-30 Angstroms,

iv. adjusting the temperature of said silicon substrate to a temperature in the range 300-500°

C.,

v. adjusting the pressure in said LPCVD reactor to a pressure in the range 50-200 mTorr,

vi. introducing precursor gases into said LPCVD reactor to deposit a layer of Ta₂ O₅ on the first SiO₂ layer, said layer of Ta₂ O₅ having a thickness in the range 30-100 Angstroms,

vii. adjusting the temperature of said silicon substrate to a temperature in the range 500-750°

C.,

viii. adjusting the pressure in said LPCVD reactor to a pressure in the range 150-350°

C.,

ix. introducing an oxide precursor gas into said LPCVD reactor and depositing a second layer of SiO₂ over said layer of Ta₂ O₅, said second layer of SiO₂ having a thickness in the range 5-30 Angstroms, thereby forming a composite layer of SiO₂ --Ta₂ O₅ --SiO₂,

x. adjusting the temperature of said silicon substrate to a temperature in the range 550-750°

C.,

xi. adjusting the pressure in said LPCVD reactor to a pressure in the range 0.7-1.1 Torr, and

xii. annealing the composite layer of SiO₂ --Ta₂ O₅ --SiO₂ for a period of 15 to 100 min, the invention further characterized in that the overall thickness of the SiO₂ --Ta₂ O₅ --SiO₂ composite layer is in the range 45-100 Angstroms.

7. The method of claim 6 wherein the atmosphere in said LPCVD reactor during step xii. is selected from the group consisting of O₂ and N₂.

8. The method of claim 6 in which the temperature in step ii. is in the range 800-900°

C., the pressure in step iii is in the range 0.8-0.9 Torr, the temperature in step iv. is in the range 375-430°

C., the pressure in step v. is in the range 75-150 mTorr, the temperature in step vii. is in the range 600-700°

C., the pressure in step viii. is in the range 200-300 mTorr, the temperature in step x. is in the range 600-700°

C., and the pressure in step xi. is in the range 0.8-1.0 Torr.

9. The method of claim 6 wherein steps iv. through ix. are repeated.