MOS transistor of semiconductor device and method of manufacturing the same

• US 6,008,097 A
• Filed: 12/11/1997
• Issued: 12/28/1999
• Est. Priority Date: 12/14/1996
• Status: Expired due to Term

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Baek, Kyu Ha, Yoon, Yong Sun, Nam, Kee Soo
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US08/989,033
• Time in Patent Office: 747 Days
• Field of Search: 438/396, 438/303, 438/234, 438/301, 257/327
• US Class Current: 438/303
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence

Abstract

The present invention relates to a MOS transistor of semiconductor device and method of manufacturing the same and, in particular, to MOS a transistor of semiconductor device and method of manufacturing the same which can reduce asymmetry of drain current due to bias of drain current, facilitate shallow junction and reduce the area to a minimum by forming a source/drain.

Claims

1. A method of manufacturing a transistor of semiconductor device, comprising the steps of:

forming two regions of a field oxide film on a semiconductor substrate;

sequentially forming a first insulation film, first silicon film and second insulation film on said semiconductor substrate and said two regions of said field oxide film, said first and second insulation film being formed by depositing an oxide;

forming a self-aligned source/drain region by sequentially etching a portion of said second insulation film, first silicon film and first insulation film between said two regions so that said remaining first silicon film becomes a pair of source/drain connection layers;

sequentially forming a second silicon film and third insulation film on the entire structure including said source/drain region, said third insulation film being formed by depositing an oxide;

forming a spacer oxide film and source/drain local electrode within said source/drain region at each pair o said pair of source/drain connection layers by sequentially etching said third insulation film and second silicon film;

forming a gate oxide film on the entire structure through a thermal oxidation process, depositing a doped polycrystal silicon on the gate oxide film, and forming a gate electrode by planarization of said doped polycrystal silicon by polishing said doped polycrystal silicon with a chemical mechanical polishing method, a source/drain being formed below each said source/drain local electrode during said thermal oxidation process; and

forming an interlayer insulation film on the entire structure in which said gate electrode is formed, and forming a metal electrode contacting said source/drain connection layer connected to said source/drain through a metal contact process.

2. A method of manufacturing a transistor of semiconductor device, comprising the steps of:

forming two regions of a field oxide film on a semiconductor substrate;

sequentially forming a first insulation film, first silicon film and second insulation film on said semiconductor substrate and said two regions of said field oxide film;

forming a self-aligned source/drain region by sequentially etching a portion of said second insulation film, first silicon film and first insulation film between said two regions so that said remaining first silicon film becomes a pair of source/drain connection layers;

sequentially forming a second silicon film and third insulation film on the entire structure including said source/drain region;

forming a spacer oxide film and source/drain local electrode within said source/drain region at each pair of said pair of source/drain connection layers by sequentially etching said third insulation film and second silicon film;

forming a gate oxide film on the entire structure through a thermal oxidation process, depositing a doped polycrystal silicon on the gate oxide film, and forming a gate electrode by planarization of said doped polycrystal silicon by polishing said doped polycrystal silicon with a chemical mechanical polishing method, a source/drain being formed below each said source/drain local electrode during said thermal oxidation process; and

forming an interlayer insulation film on the entire structure in which said gate electrode is formed, and forming a metal electrode contacting said source/drain connection layer connected to said source/drain through a metal contact process,

wherein said step of forming a gate oxide film further comprises forming said source/drain when an impurity contained in said source/drain connection layer is diffused into said semiconductor substrate using the source/drain local electrode as a diffusion path during the thermal oxidation process for forming said gate oxide film and activating said diffused impurity during said depositing a doped polycrystal silicon on the gate oxide film for forming said gate electrode.