Ultra shallow junction formation using amorphous silicon layer

• US 6,008,098 A
• Filed: 10/04/1996
• Issued: 12/28/1999
• Est. Priority Date: 10/04/1996
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Pramanick, Shekhar, Ng, Che-Hoo
• Primary Examiner(s): BOOTH, RICHARD A
• Application Number:
  US08/726,113
• Time in Patent Office: 1,180 Days
• Field of Search: 437/24, 437/41, 437/162, 437/931, 437/27, 438/527-529, 438/303, 438/305
• US Class Current: 438/305
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method of achieving shallow junctions in a semiconductor device is achieved by providing an amorphous silicon layer over an epitaxial layer, implanting ions into the amorphous silicon layer, and annealing the resulting device to recrystallize the amorphous silicon layer and drive in the implanted ions to a shallow depth less than the depth of the amorphous silicon layer.

Claims

1. A method of fabricating a semiconductor device comprising:

providing a silicon body;

providing an insulator layer over the silicon body;

providing a conductor material over the insulator layer to form a gate electrode over the silicon body;

providing an amorphous silicon layer of a predetermined depth at the surface of the silicon body, wherein the act of providing an amorphous silicon layer follows the act of providing a conductor material;

providing spacers on the insulator adjacent the gate electrode;

using the gate electrode and the spacers as masking material, introducing a first impurity into the silicon body through the insulator layer;

removing said spacers;

providing a second impurity in the amorphous silicon layer; and

diffusing the second impurity in the amorphous silicon layer into to a depth less than said predetermined depth.

2. The method of claim 1 and further providing that the amorphous silicon layer becomes crystalline.

3. The method of claim 1 wherein the step of providing the second impurity in the amorphous silicon layer comprises implanting ions in the amorphous silicon layer.

4. The method of claim 1 wherein the step of diffusing the second impurity comprises annealing.

5. The method of claim 2 wherein the step of providing that the amorphous silicon layer becomes crystalline comprises annealing.

6. The method of claim 1 wherein the step of providing a second impurity in the amorphous silicon layer comprises providing boron ions in the amorphous silicon layer.

7. The method of claim 1 wherein the step of providing a second impurity in the amorphous silicon layer comprises providing arsenic ions in the amorphous silicon layer.

8. The method of claim 1 wherein the step of providing a second impurity in the amorphous silicon layer comprises providing phosphorous ions in the amorphous silicon layer.

9. The method of claim 1 wherein the step of providing a second impurity in the amorphous silicon layer comprises providing antimony ions in the amorphous silicon layer.

10. A method of fabricating a semiconductor device comprising:

providing a silicon body;

providing an oxide layer over the silicon body;

providing a polysilicon layer over the oxide layer;

implanting ions through the polysilicon layer, oxide layer and into the silicon body to form an amorphous silicon layer of a predetermined depth under the oxide layer;

patterning the polysilicon layer and oxide layer to form a gate electrode and to expose a portion of the amorphous silicon layer;

providing oxide spacers adjacent to the gate electrode;

using the gate electrode and the oxide spacers as masking material, introducing a first impurity into the silicon body;

removing said oxide spacers;

implanting a second impurity into the amorphous silicon layer; and

diffusing the second impurity implanted in the amorphous silicon layer to a depth less than said predetermined depth.

11. The method of claim 10 wherein the step of diffusing the second impurity implanted into the amorphous silicon layer comprises an annealing step to cause the second impurity implanted into the amorphous silicon layer to diffuse and to cause the amorphous silicon layer to become crystalline.

12. The method of claim 10 wherein the step of implanting a second impurity into the amorphous silicon layer comprises implanting boron ions in the amorphous silicon layer.

13. The method of claim 10 wherein the step of implanting a second impurity into the amorphous silicon layer comprises implanting arsenic ions into the amorphous silicon layer.

14. The method of claim 10 wherein the step of implanting a second impurity into the amorphous silicon layer comprises implanting phosphorous ions into the amorphous silicon layer.

15. The method of claim 10 wherein the step of implanting a second impurity into the amorphous silicon layer comprises implanting antimony ions into the amorphous silicon layer.