Membrane dielectric isolation IC fabrication

• US 6,008,126 A
• Filed: 02/23/1998
• Issued: 12/28/1999
• Est. Priority Date: 04/08/1992
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn Joseph
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Lebentritt, Michael
• Application Number:
  US09/028,081
• Time in Patent Office: 673 Days
• Field of Search: 438/667, 438/668
• US Class Current: 438/667
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/5381 Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Claims

1. A method of forming an interconnect circuit comprising the steps of:

providing a free standing membrane formed of at least one layer of low stress dielectric; and

forming a pattern of electrically conductive traces on the dielectric.

2. The method of claim 1, wherein the step of providing comprises:

providing a dielectric substrate less than about 100 microns thick;

forming films of polycrystalline silicon on both surfaces of the substrate; and

etching away a portion of the substrate;

wherein the pattern of electrically conductive traces are formed by patterning a metal film deposited on at least one of the films of polycrystalline silicon.

3. A method of forming an interconnect circuit comprising the steps of:

forming a free standing membrane having at least one layer of low stress dielectric; and

forming a pattern of electrically conductive traces on the dielectric.

4. The method of claim 3, wherein the step of forming a free standing membrane comprises:

providing a dielectric substrate less than about 100 mils thick;

forming films of polycrystalline silicon on both surfaces of the substrate; and

etching away a portion of the substrate;

wherein the pattern of electrically conductive traces are formed by patterning a metal film deposited on at least one of the films of polycrystalline silicon.